Displaying 5 results from an estimated 5 matches for "beinst".
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reinst
2009 Jul 04
2
[LLVMdev] Help on DAG pattern matching string
...kes a pointers and an offset and returns the new
pointer value:
def DefReg : Register<"r">;
def PtrReg : Register<"ptr">;
def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
pattern> : Instruction { /* assign arguments to class members */ }
def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
I32RC:$src2), "PADD",
[(set P32RC:$dst, (a...
2009 Jul 04
0
[LLVMdev] Help on DAG pattern matching string
...returns the new
> pointer value:
>
> def DefReg : Register<"r">;
> def PtrReg : Register<"ptr">;
> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
> pattern> : Instruction { /* assign arguments to class members */ }
> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
> I32RC:$src2), "PADD",
> [(s...
2009 Jul 06
2
[LLVMdev] Help on DAG pattern matching string
...nter value:
>>
>> def DefReg : Register<"r">;
>> def PtrReg : Register<"ptr">;
>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
>> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
>> pattern> : Instruction { /* assign arguments to class members */ }
>> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
>> I32RC:$src2), "PADD",
>>...
2009 Jul 06
0
[LLVMdev] Help on DAG pattern matching string
...>>> def DefReg : Register<"r">;
>>> def PtrReg : Register<"ptr">;
>>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
>>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
>>> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
>>> pattern> : Instruction { /* assign arguments to class members */ }
>>> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
>>> I32RC:$src2), "PADD",
>>>...
2018 May 10
2
LLVM SCEV isAddRecNeverPoison and strength reduction
+CC llvm-dev
On Tue, May 8, 2018 at 2:34 AM, Gal Zohar <Gal.Zohar at ceva-dsp.com> wrote:
> I noticed that SCEV, when trying to perform strength reduction, doesn’t use
> the ability to prove an induction variable does not signed/unsigned wrap due
> to infinite loops.
>
> Is there an easy way to use the isAddRecNeverPoison function when
> determining if strength reduction