Displaying 20 results from an estimated 54 matches for "begin_ring".
2009 Dec 30
4
[PATCH 1/3] nv50: remove vtxbuf stateobject after a referenced vtxbuf is mapped
- This avoids problematic "reloc'ed while mapped" messages and
some associated corruption as well.
Signed-off-by: Maarten Maathuis <madman2003 at gmail.com>
---
src/gallium/drivers/nouveau/nouveau_screen.c | 21 +++++++++++++++++++++
src/gallium/drivers/nouveau/nouveau_screen.h | 3 +++
src/gallium/drivers/nouveau/nouveau_stateobj.h | 13 +++++++++++++
2009 Nov 04
1
[PATCH] nv10/exa: Spring-cleaning
...- (log2h<<16) |
- (1<<12) | /* lod == 1 */
- 0x51 /* UNK */;
+ NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE |
+ NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE |
+ log2i(w) << 20 | log2i(h) << 16 |
+ 1 << 12 | /* lod == 1 */
+ get_tex_format(pict) |
+ 0x51 /* UNK */;
BEGIN_RING(chan, celsius, NV10TCL_TX_OFFSET(unit), 1);
OUT_RELOCl(chan, bo, delta, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
- /* if repeat is set we're always handling a 1x1 texture with ARGB/XRGB destination,
- in that case we change the format to use the POT (swizzled) matching format */
- if (Pict->re...
2009 Dec 26
2
[PATCH 1/3] drm/nouveau: Allocate a per-channel instance of NV_SW.
...nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
+ if (ret)
+ return ret;
+
/* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
if (ret)
@@ -87,6 +97,13 @@ nouveau_dma_init(struct nouveau_channel *chan)
BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
OUT_RING(chan, NvNotify0);
+ /* Initialise NV_SW */
+ ret = RING_SPACE(chan, 2);
+ if (ret)
+ return ret;
+ BEGIN_RING(chan, NvSubSw, 0, 1);
+ OUT_RING(chan, NvSw);
+
/* Sit back and pray the channel works.. */
FIRE_RING(chan);...
2010 Jan 18
1
[PATCH 1/2] nv30-nv40: Rewrite primitive splitting and emission
...+static inline void
+nv30_primitive_start_vertex(struct nv30_primitive* prim)
+{
+ struct nv30_screen *screen = prim->nv30->screen;
+ struct nouveau_channel *chan = screen->base.channel;
+ struct nouveau_grobj *rankine = screen->rankine;
+
+ if(prim->startv & START_INDEX)
+ {
+ BEGIN_RING(chan, rankine, NV34TCL_VB_INDEX_BATCH, 1);
+ OUT_RING (chan, (prim->startv & ~START_INDEX));
+ }
+ else
+ {
+ BEGIN_RING(chan, rankine, NV34TCL_VB_ELEMENT_U32, 1);
+ OUT_RING (chan, prim->startv);
+ }
+}
+
+static inline unsigned
+nv30_primitive_begin(struct nv30_primitive* prim, uns...
2009 Oct 22
1
[PATCH] nv04-nv40/exa: Reorder the commands in PrepareCopy to match the blob.
...c
@@ -197,16 +197,9 @@ NV04EXAPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int dx, int dy,
return FALSE;
planemask |= ~0 << pDstPixmap->drawable.bitsPerPixel;
- if (planemask != ~0 || alu != GXcopy) {
- if (pDstPixmap->drawable.bitsPerPixel == 32)
- return FALSE;
- BEGIN_RING(chan, blit, NV04_IMAGE_BLIT_OPERATION, 1);
- OUT_RING (chan, 1); /* ROP_AND */
- NV04EXASetROP(pScrn, alu, planemask);
- } else {
- BEGIN_RING(chan, blit, NV04_IMAGE_BLIT_OPERATION, 1);
- OUT_RING (chan, 3); /* SRCCOPY */
- }
+ if ((planemask != ~0 || alu != GXcopy)
+ && pDstPixma...
2009 Jul 02
1
[PATCH] drm/nv50: wait for fifo completion when needed
...ut;
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index d8e8f1b..dba8b93 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -176,6 +176,7 @@ static int nv50_crtc_set_dither(struct nouveau_crtc *crtc, bool update)
BEGIN_RING(evo, 0, NV50_UPDATE_DISPLAY, 1);
OUT_RING (evo, 0);
FIRE_RING (evo);
+ RING_WAIT (evo);
}
return 0;
@@ -294,6 +295,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *crtc, int scaling_mode, bool update)
BEGIN_RING(evo, 0, NV50_UPDATE_DISPLAY, 1);
OUT_RING (evo, 0);
FIRE_RING (evo...
2010 May 31
1
[PATCH] nv50/exa: use dual-source blending for component-alpha composite
...ged, 28 insertions(+), 56 deletions(-)
diff --git a/src/nv50_accel.c b/src/nv50_accel.c
index 1218e18..db8c744 100644
--- a/src/nv50_accel.c
+++ b/src/nv50_accel.c
@@ -213,7 +213,7 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn)
OUT_RING (chan, (0 << NV50TCL_CB_DEF_SET_BUFFER_SHIFT) | 0x4000);
BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
OUT_RING (chan, 0);
- BEGIN_RING_NI(chan, tesla, NV50TCL_CB_DATA(0), 16);
+ BEGIN_RING_NI(chan, tesla, NV50TCL_CB_DATA(0), 22);
OUT_RING (chan, 0x80000000);
OUT_RING (chan, 0x90000004);
OUT_RING (chan, 0x82030210);
@@ -228,36 +228,14 @@ NVAccelInitNV50T...
2009 Apr 08
0
[PATCH/Gallium] nv50: update nv50_clear to new interface
...0;
sc.maxx = fb.width;
sc.maxy = fb.height;
@@ -59,28 +88,30 @@ nv50_clear(struct pipe_context *pipe, struct pipe_surface *ps,
nv50_state_validate(nv50);
- switch (ps->format) {
- case PIPE_FORMAT_A8R8G8B8_UNORM:
+ if (fb.nr_cbufs > 0) {
+ /* Does this clear all color buffers ? */
BEGIN_RING(chan, tesla, 0x0d80, 4);
- OUT_RINGf (chan, ubyte_to_float((clearValue >> 16) & 0xff));
- OUT_RINGf (chan, ubyte_to_float((clearValue >> 8) & 0xff));
- OUT_RINGf (chan, ubyte_to_float((clearValue >> 0) & 0xff));
- OUT_RINGf (chan, ubyte_to_float((clearValue >&...
2009 Apr 10
0
[PATCH/Gallium] nv50_clear again (might work better)
...50TCL_CLEAR_COLOR_BITS(i) (0x3c + (0x40 * (i)))
+
void
nv50_clear(struct pipe_context *pipe, unsigned buffers,
const float *rgba, double depth, unsigned stencil)
@@ -40,26 +47,32 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers,
return;
if (buffers & PIPE_CLEAR_COLOR) {
- BEGIN_RING(chan, tesla, NV50TCL_CLEAR_COLOR(0), 4*fb->nr_cbufs);
- for (i = 0; i < fb->nr_cbufs; i++) {
- OUT_RING (chan, fui(rgba[0]));
- OUT_RING (chan, fui(rgba[1]));
- OUT_RING (chan, fui(rgba[2]));
- OUT_RING (chan, fui(rgba[3]));
- }
- mode |= 0x3c;
+ assert(fb->nr_cbufs >...
2009 Dec 05
1
[PATCH] nouveau: avoid running out of relocs (attempt 4)
.../nv04_surface_2d.c
@@ -133,6 +133,9 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
assert(sub_w == w || util_is_pot(sub_w));
assert(sub_h == h || util_is_pot(sub_h));
+ MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
+ ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
+
BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
OUT_RELOCo(chan, dst_bo,
NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
@@ -202,7 +205,7 @@ nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
unsigned src_offset = src->offset + sy * src_pitch +...
2009 Oct 14
0
[PATCH 3/7] nv50: submit user vbo data through the fifo
...nv50_context(pipe);
struct nouveau_channel *chan = nv50->screen->tesla->channel;
struct nouveau_grobj *tesla = nv50->screen->tesla;
+ boolean ret;
nv50_state_validate(nv50);
@@ -142,17 +155,22 @@ nv50_draw_arrays(struct pipe_context *pipe, unsigned mode, unsigned start,
BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
OUT_RING (chan, nv50_prim(mode));
- BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
- OUT_RING (chan, start);
- OUT_RING (chan, count);
+
+ if (nv50->vbo_fifo)
+ ret = nv50_push_arrays(nv50, start, count);
+ else {
+ BEGIN_RING(chan, tesla,...
2011 Oct 10
2
2 remaining patches in my patch queue that can be merged
Hi,
Here I post these 2 misc patches.
Best regards,
Maxim Levitsky
2010 Apr 20
1
[PATCH] nv30/exa : cleanup from nv40 exa
...NE_MINUS_SRC_COLOR);
+ if (dblend == DF(SRC_ALPHA)) {
+ dblend = DF(SRC_COLOR);
+ } else if (dblend == DF(ONE_MINUS_SRC_ALPHA)) {
+ dblend = DF(ONE_MINUS_SRC_COLOR);
}
}
- if (sblend == BF(ONE) && dblend == BF(ZERO)) {
+ if (sblend == SF(ONE) && dblend == DF(ZERO)) {
BEGIN_RING(chan, rankine, NV34TCL_BLEND_FUNC_ENABLE, 1);
OUT_RING (chan, 0);
} else {
BEGIN_RING(chan, rankine, NV34TCL_BLEND_FUNC_ENABLE, 3);
OUT_RING (chan, 1);
- OUT_RING (chan, (sblend << 16) | sblend);
- OUT_RING (chan, (dblend << 16) | dblend);
+ OUT_RING (chan, sblend);
+...
2009 Dec 05
0
[PATCH] nouveau: avoid running out of relocs (attempt 3)
.../nv04_surface_2d.c
@@ -133,6 +133,9 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
assert(sub_w == w || util_is_pot(sub_w));
assert(sub_h == h || util_is_pot(sub_h));
+ MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
+ ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
+
BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
OUT_RELOCo(chan, dst_bo,
NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
@@ -202,7 +205,7 @@ nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
unsigned src_offset = src->offset + sy * src_pitch +...
2009 Dec 28
3
Synchronization mostly missing?
...aining artifacts may be due to missing 2D engine
synchronization, but I'm not sure how that works.
Note that this causes the CPU to wait for rendering, which is not the
correct solution
static void nv40_sync(struct nv40_context *nv40)
{
nouveau_notifier_reset(nv40->screen->sync, 0);
// BEGIN_RING(curie, 0x1d6c, 1);
// OUT_RING(0x5c0);
// static int value = 0x23;
// BEGIN_RING(curie, 0x1d70, 1);
// OUT_RING(value++);
BEGIN_RING(curie, NV40TCL_NOTIFY, 1);
OUT_RING(0);
BEGIN_RING(curie, NV40TCL_NOP, 1);
OUT_RING(0);
FIRE_RING(NULL);
nouveau_notifier_wait_status(nv40->screen->...
2009 Dec 13
3
[PATCH] nouveau: avoid running out of relocs (attempt 5)
.../nv04_surface_2d.c
@@ -133,6 +133,9 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
assert(sub_w == w || util_is_pot(sub_w));
assert(sub_h == h || util_is_pot(sub_h));
+ MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
+ ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
+
BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
OUT_RELOCo(chan, dst_bo,
NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
@@ -202,7 +205,7 @@ nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
unsigned src_offset = src->offset + sy * src_pitch +...
2009 Dec 25
1
[PATCH] drm/nv50: synchronize user channel after buffer object move on kernel channel
...NULL);
+ if (ret)
+ return ret;
+
+ ret = nouveau_notifier_alloc(chan, NvNotify1, 32, &chan->sync_ntfy);
+ if (ret)
+ return ret;
+ }
+
/* Map push buffer */
ret = nouveau_bo_map(chan->pushbuf_bo);
if (ret)
@@ -87,6 +104,15 @@ nouveau_dma_init(struct nouveau_channel *chan)
BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
OUT_RING(chan, NvNotify0);
+ /* Bind NvSw to channel. */
+ if (dev_priv->card_type >= NV_50) {
+ ret = RING_SPACE(chan, 2);
+ if (ret)
+ return ret;
+ BEGIN_RING(chan, NvSubSw, 0, 1);
+ OUT_RING(chan, NvSw);
+ }
+
/* Sit...
2010 Jan 03
1
[PATCH] nouveau: nv50: fix ->pseudo_palette usage
...uveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *chan = dev_priv->channel;
+ uint32_t color;
if (info->state != FBINFO_STATE_RUNNING)
return;
@@ -31,7 +32,12 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
OUT_RING(chan, 1);
}
BEGIN_RING(chan, NvSub2D, 0x0588, 1);
- OUT_RING(chan, rect->color);
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
+ info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
+ color = ((uint32_t *)info->pseudo_palette)[rect->color];
+ } else
+ color = rect->color;
+ OUT_RING(chan, color);
BEG...
2010 Apr 09
1
SERIALIZE command
Hi all,
I am trying to use the 0x110 SERIALIZE (or 0x108 WAIT_FOR_IDLE?) command to
barrier the PGRAPH commands.
Unfortunately, I do not find any examples either in nouveau or gallium.
If it plays just a barrier, I guess it should work by something like (in
case of m2mf):
BEGIN_RING(chan, m2mf, 0x110, 1);
OUT_RING(chan, 1);
Otherwise, it may actually play to serialize some commands, then I would
rather use as follows:
BEGIN_RING(chan, m2mf, 0x110, 1);
OUT_RING(chan, NUMBER_OF_FOLLOWING_COMMANDS);
I have tried both approaches, and the application runs without any problems,
bu...
2011 Oct 09
11
[PATCH 01/10]: nouveau: assorted fixes
Hi,
Here is my patch queue I accumulated over quite a long time.
Patches 1-6 are bugfixes, and rest is mostly RFC.
Comments are welcome.
Best regards,
Maxim Levitsky