Displaying 20 results from an estimated 87 matches for "begin_nv04".
2015 Mar 21
0
[PATCH] use defined method names where available
...4 ++--
src/nvc0_exa.c | 2 +-
10 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/src/nv10_exa.c b/src/nv10_exa.c
index 78bc739..7daa281 100644
--- a/src/nv10_exa.c
+++ b/src/nv10_exa.c
@@ -697,9 +697,9 @@ NVAccelInitNV10TCL(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0);
}
- BEGIN_NV04(push, SUBC_3D(0x290), 1);
+ BEGIN_NV04(push, NV10_3D(UNK0290), 1);
PUSH_DATA (push, (0x10<<16)|1);
- BEGIN_NV04(push, SUBC_3D(0x3f4), 1);
+ BEGIN_NV04(push, NV10_3D(UNK03F4), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV04_GRAPH(3D, NOP), 1);
@@ -707,12 +707,12 @@ NVAccelInitNV10TCL(Sc...
2014 Feb 13
2
[PATCH] nv50: make sure to clear _all_ layers of all attachments
...uveau/nv50/nv50_state_validate.c
index f953422..100d02d 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -65,6 +65,7 @@ nv50_validate_fb(struct nv50_context *nv50)
PUSH_DATA (push, sf->height);
BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
PUSH_DATA (push, array_mode | array_size);
+ nv50->rt_array_mode = array_mode | array_size;
} else {
PUSH_DATA (push, 0);
PUSH_DATA (push, 0);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium...
2014 May 21
2
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...6e68fb8 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> @@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
>
> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>
> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
> + PUSH_DATA (push, ( width << 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);...
2014 Feb 04
2
[PATCH 1/3] nv50: rework primid logic
Functionally identical but much simpler. Should also better integrate
with future layer/viewport changes/fixes.
Cc: 10.1 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Not *strictly* necessary in stable, but it will make backporting later fixes
easier. No regressions in piglit.
src/gallium/drivers/nouveau/nv50/nv50_program.c | 5
2014 May 20
0
[PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...nv50/nv50_surface.c
index 1f37527..6e68fb8 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
+ BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, ( width << 16) | dstx);
+ PUSH_DATA (push, (height << 16) | dsty);
+ BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
+ PUSH_DATA (push, 8192 << 16);
+ PUSH_DATA (push, 8192 << 16);
+ nv50->scissors_di...
2014 May 21
0
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
>> +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
>> @@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
>>
>> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>>
>> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
>> + PUSH_DATA (push, ( width << 16) | dstx);
>> + PUSH_DATA (push, (height << 16) | dsty);
>> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
>> + PUSH_DATA (push, 8192 << 16);
>> + PUSH_DATA (push...
2015 May 24
2
[Mesa-dev] [PATCH 2/2] nv30: fix clip plane uploads and enable changes
...,15 +272,13 @@ nv30_validate_clip(struct nv30_context *nv30)
> uint32_t clpd_enable = 0;
>
> for (i = 0; i < 6; i++) {
> - if (nv30->rast->pipe.clip_plane_enable & (1 << i)) {
> - if (nv30->dirty & NV30_NEW_CLIP) {
> - BEGIN_NV04(push, NV30_3D(VP_UPLOAD_CONST_ID), 5);
> - PUSH_DATA (push, i);
> - PUSH_DATAp(push, nv30->clip.ucp[i], 4);
> - }
> -
> - clpd_enable |= 1 << (1 + 4*i);
> + if (nv30->dirty & NV30_NEW_CLIP) {
> + BEGIN_NV04(push...
2014 Feb 13
2
[PATCH] nouveau: fix chipset checks for nv1a by using the oclass instead
...rs & BUFFER_BIT_DEPTH) && ctx->Depth.Mask) {
- if (context_chipset(ctx) >= 0x17)
+ if (context_eng3d(ctx)->oclass >= NV17_3D_CLASS)
nv17_zclear(ctx, &buffers);
else
nv10_zclear(ctx, &buffers);
@@ -245,7 +245,7 @@ nv10_hwctx_init(struct gl_context *ctx)
BEGIN_NV04(push, NV04_GRAPH(3D, NOP), 1);
PUSH_DATA (push, 0);
- if (context_chipset(ctx) >= 0x17) {
+ if (context_eng3d(ctx)->oclass >= NV17_3D_CLASS) {
BEGIN_NV04(push, NV17_3D(UNK01AC), 2);
PUSH_DATA (push, fifo->vram);
PUSH_DATA (push, fifo->vram);
@@ -257,7 +257,7 @@ nv10_hwct...
2015 Jan 02
2
[PATCH] nv50: enable texture compression
...reen *screen)
+nv50_screen_init_hwctx(struct nouveau_device *dev, struct nv50_screen *screen)
{
struct nouveau_pushbuf *push = screen->base.pushbuf;
struct nv04_fifo *fifo;
@@ -449,6 +449,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
PUSH_DATA (push, 0x18);
}
+ BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
+ PUSH_DATA(push, dev->drm_version >= 0x01000101);
+
+ BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
+ for (i = 0; i < 8; ++i)
+ PUSH_DATA(push, dev->drm_version >= 0x01000101);
+
BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
PUS...
2015 May 24
2
[Mesa-dev] [PATCH 2/2] nv30: fix clip plane uploads and enable changes
...p(struct nv30_context *nv30)
>>> uint32_t clpd_enable = 0;
>>> for (i = 0; i < 6; i++) {
>>> - if (nv30->rast->pipe.clip_plane_enable & (1 << i)) {
>>> - if (nv30->dirty & NV30_NEW_CLIP) {
>>> - BEGIN_NV04(push, NV30_3D(VP_UPLOAD_CONST_ID), 5);
>>> - PUSH_DATA (push, i);
>>> - PUSH_DATAp(push, nv30->clip.ucp[i], 4);
>>> - }
>>> -
>>> - clpd_enable |= 1 << (1 + 4*i);
>>> + if (nv30->dirty &...
2014 Jan 17
2
[PATCH] nv50, nvc0: only clear out the buffers that we were asked to clear
...NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
- NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
}
if (buffers & PIPE_CLEAR_DEPTH) {
@@ -425,12 +422,16 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers,
mode |= NV50_3D_CLEAR_BUFFERS_S;
}
- BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
- PUSH_DATA (push, mode);
-
- for (i = 1; i < fb->nr_cbufs; i++) {
+ if (mode) {
BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
- PUSH_DATA (push, (i << 6) | 0x3c);
+ PUSH_DATA (push, mode);
+ }
+
+ for (i = 0; i < fb->nr_...
2014 Dec 31
0
[PATCH] nv50,nvc0: set vertex id base to index_bias
...ium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index ff08734..2d8347b 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -608,6 +608,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
PUSH_DATA (push, 1);
+ BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
+ PUSH_DATA (push, 0);
+ if (screen->base.class_3d >= NV84_3D_CLASS) {
+ BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+ PUSH_DATA (push, 0);
+ }
+
PUSH_KICK...
2015 May 24
2
[Mesa-dev] [PATCH 2/2] nv30: fix clip plane uploads and enable changes
...gt;> uint32_t clpd_enable = 0;
>>>>> for (i = 0; i < 6; i++) {
>>>>> - if (nv30->rast->pipe.clip_plane_enable & (1 << i)) {
>>>>> - if (nv30->dirty & NV30_NEW_CLIP) {
>>>>> - BEGIN_NV04(push, NV30_3D(VP_UPLOAD_CONST_ID), 5);
>>>>> - PUSH_DATA (push, i);
>>>>> - PUSH_DATAp(push, nv30->clip.ucp[i], 4);
>>>>> - }
>>>>> -
>>>>> - clpd_enable |= 1 << (1 + 4*i);
>...
2015 May 24
2
[PATCH 1/2] nv30: avoid doing extra work on clear and hitting unexpected states
...rc/gallium/drivers/nouveau/nv30/nv30_draw.c
@@ -129,7 +129,7 @@ nv30_render_draw_elements(struct vbuf_render *render,
NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, 0);
}
- if (!nv30_state_validate(nv30, FALSE))
+ if (!nv30_state_validate(nv30, ~0, FALSE))
return;
BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
@@ -174,7 +174,7 @@ nv30_render_draw_arrays(struct vbuf_render *render, unsigned start, uint nr)
NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, 0);
}
- if (!nv30_state_validate(nv30, FALSE))
+ if (!nv30_state_validate(nv30, ~0, FALSE))...
2013 Jun 30
0
[PATCH v2] nv50: H.264/MPEG2 decoding support via VP2, available on NV84-NV96, NVA0
...0, 0, 1024, 1);
+
+ PUSH_SPACE(screen->pushbuf, 5);
+ PUSH_REFN(screen->pushbuf, dec->fence, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+ /* The clear_render_target is done via 3D engine, so use it to write to a
+ * sempahore to indicate that it's done.
+ */
+ BEGIN_NV04(screen->pushbuf, NV50_3D(QUERY_ADDRESS_HIGH), 4);
+ PUSH_DATAh(screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, 1);
+ PUSH_DATA (screen->pushbuf, 0xf010);
+ PUSH_KICK (screen-&g...
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2013 Jun 27
4
[PATCH] nv50: H.264/MPEG2 decoding support via VP2, available on NV84-NV96, NVA0
...;
+
+ PUSH_SPACE(screen->pushbuf, 5);
+ fence_ref[0].bo = dec->fence;
+ nouveau_pushbuf_refn(screen->pushbuf, fence_ref, 1);
+ /* The clear_render_target is done via 3D engine, so use it to write to a
+ * sempahore to indicate that it's done.
+ */
+ BEGIN_NV04(screen->pushbuf, SUBC_3D(0x1b00), 4);
+ PUSH_DATAh(screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, 1);
+ PUSH_DATA (screen->pushbuf, 0xf010);
+ PUSH_KICK (screen->pushbuf);...
2014 Mar 06
0
[RFC PATCH] nv50: adjust blit_3d logic
...index dc6d628..216e667 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -1069,7 +1069,7 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
PUSH_DATAf(push, y0);
PUSH_DATAf(push, z);
BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
- PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_x);
+ PUSH_DATAf(push, 16384/* << nv50_miptree(dst)->ms_x*/);
PUSH_DATAf(push, 0.0f);
BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
PUSH_DATAf(push, x0);
@@ -107...
2015 May 25
3
[PATCH 1/2] nv30/draw: rework some of the output vertex buffer logic
...;buffer), r->offset + r->vtxptr[i],
- NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, 0);
+ NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, NV30_3D_VTXBUF_DMA1);
}
if (!nv30_state_validate(nv30, ~0, FALSE))
return;
+ if (nv30->base.vbo_dirty) {
+ BEGIN_NV04(push, NV30_3D(VTX_CACHE_INVALIDATE_1710), 1);
+ PUSH_DATA (push, 0);
+ nv30->base.vbo_dirty = FALSE;
+ }
+
BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
PUSH_DATA (push, r->prim);
@@ -178,6 +188,12 @@ nv30_render_draw_arrays(struct vbuf_render *render, unsigned start,...
2014 Oct 21
0
[PATCH v2] nv50: Handle ARB_conditional_render_inverted and enable it
...ate");
+ cond = NV50_3D_COND_MODE_ALWAYS;
+ break;
+ }
+ }
nv50->cond_query = pq;
nv50->cond_cond = condition;
+ nv50->cond_condmode = cond;
nv50->cond_mode = mode;
- PUSH_SPACE(push, 9);
-
if (!pq) {
+ PUSH_SPACE(push, 2);
BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
- PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
+ PUSH_DATA (push, cond);
return;
}
- q = nv50_query(pq);
- if (mode == PIPE_RENDER_COND_WAIT ||
- mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
+ if (wait) {
BEGIN_NV04(push, SUBC_3D(...