search for: begin_imc0

Displaying 6 results from an estimated 6 matches for "begin_imc0".

2016 Oct 16
0
[PATCH 3/5] nvc0: rename BEGIN_IMC0 to IMMED_NVC0
...file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/nouveau_local.h b/src/nouveau_local.h index 3de69a2..dd49395 100644 --- a/src/nouveau_local.h +++ b/src/nouveau_local.h @@ -237,7 +237,7 @@ BEGIN_NIC0(struct nouveau_pushbuf *push, int subc, int mthd, int size) } static inline void -BEGIN_IMC0(struct nouveau_pushbuf *push, int subc, int mthd, int data) +IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, int data) { PUSH_DATA (push, 0x80000000 | (data << 16) | (subc << 13) | (mthd / 4)); } -- 2.7.3
2020 May 20
2
[PATCH] nouveau/hmm: fix migrate zero page to GPU
...t; 0) /* DST_X_CONST_A */ | + (5 << 4) /* DST_Y_CONST_B */ | + (3 << 16) /* COMPONENT_SIZE_FOUR */ | + (1 << 24) /* NUM_DST_COMPONENTS_TWO */; + int ret; + + ret = RING_SPACE(chan, 12); + if (ret) + return ret; + + switch (dst_aper) { + case NOUVEAU_APER_VRAM: + BEGIN_IMC0(chan, NvSubCopy, 0x0264, 0); + break; + case NOUVEAU_APER_HOST: + BEGIN_IMC0(chan, NvSubCopy, 0x0264, 1); + break; + default: + return -EINVAL; + } + launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ + + BEGIN_NVC0(chan, NvSubCopy, 0x0700, 3); + OUT_RING(chan, 0); + OUT_RING(chan, 0); + OUT_R...
2017 Mar 13
0
[ANNOUNCE] xf86-video-nouveau 1.0.14
Ilia Mirkin (7):       exa: add GM10x acceleration support       hwdefs: update nvc0_3d, add gm107_texture for new TIC format       nvc0: make use of the new hwdefs for TEX_CB_INDEX       nvc0: rename BEGIN_IMC0 to IMMED_NVC0       nvc0: refactor TIC uploads to allow different specifics per generation       copy: add maxwell/pascal copy engine classes       recognize and accelerate GM20x Lyude (2):       Consider CRTCs disabled when DPMS is off       Bump version to 1.0.14 git tag: xf86-video-nouveau-1.0...
2017 Mar 13
0
[ANNOUNCE] xf86-video-nouveau 1.0.14
Ilia Mirkin (7):       exa: add GM10x acceleration support       hwdefs: update nvc0_3d, add gm107_texture for new TIC format       nvc0: make use of the new hwdefs for TEX_CB_INDEX       nvc0: rename BEGIN_IMC0 to IMMED_NVC0       nvc0: refactor TIC uploads to allow different specifics per generation       copy: add maxwell/pascal copy engine classes       recognize and accelerate GM20x Lyude (2):       Consider CRTCs disabled when DPMS is off       Bump version to 1.0.14 git tag: xf86-video-nouveau-1.0...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++---------------- 2 files changed, 892 insertions(+), 340 deletions(-) create mode 100644 src/hwdefs/gm107_texture.xml.h diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
...GP10x should be very easy to add, but without someone to actually test I didn't want to claim support for it. Ilia Mirkin (7): exa: add GM10x acceleration support hwdefs: update nvc0_3d, add gm107_texture for new TIC format nvc0: make use of the new hwdefs for TEX_CB_INDEX nvc0: rename BEGIN_IMC0 to IMMED_NVC0 nvc0: refactor TIC uploads to allow different specifics per generation copy: add maxwell/pascal copy engine classes recognize and accelerate GM20x src/Makefile.am | 17 + src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 8...