search for: begin_1ic0

The main patches are from Christoph. Unfortunately they're a little beyond my understanding of all the vertex-related details, but they generally seemed fine. I'm just going to push these unless someone steps up to review them. Christoph Bumiller (2): nvc0: add support for indirect drawing nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYS Ilia Mirkin (1): nouveau: check if

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/drivers/nouveau/nv50/nv50_context.c | 22 ++++++++++++++++++- src/gallium/drivers/nouveau/nv50/nv50_context.h | 1 + src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 29 ++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c

...h, txc->offset + (tic->id * 32)); PUSH_DATA (push, txc->offset + (tic->id * 32)); - BEGIN_NVC0(push, NVE4_P2MF(LINE_LENGTH_IN), 2); + BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2); PUSH_DATA (push, 32); PUSH_DATA (push, 1); - BEGIN_1IC0(push, NVE4_P2MF(EXEC), 9); + BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9); PUSH_DATA (push, 0x1001); PUSH_DATAp(push, &tic->tic[0], 8); @@ -437,13 +437,13 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s) tsc->id = nvc0_screen_tsc_alloc(nvc0-&gt...

...dpix, if (!PUSH_SPACE(push, 64)) return; + if (pNv->dev->chipset >= 0x110) { + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); + PUSH_DATA (push, 256); + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA)); + BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1); + PUSH_DATA (push, 0x80); + + PUSH_DATAf(push, dx); + PUSH_DATAf(push, dy + (h * 2)); + PUSH_DATAf(push, 0); + PUSH_DATAf(push, 1); + PUSH_DATAf(push, sx); + PUSH_DATAf(push, sy + (h * 2)); + PUSH_DATAf(push, mx); + PUSH_DATAf(push, my + (h * 2)...

...dpix, if (!PUSH_SPACE(push, 64)) return; + if (pNv->dev->chipset >= 0x110) { + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); + PUSH_DATA (push, 256); + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA)); + BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1); + PUSH_DATA (push, 0x80); + + PUSH_DATAf(push, dx); + PUSH_DATAf(push, dy + (h * 2)); + PUSH_DATAf(push, 0); + PUSH_DATAf(push, 1); + PUSH_DATAf(push, sx); + PUSH_DATAf(push, sy + (h * 2)); + PUSH_DATAf(push, mx); + PUSH_DATAf(push, my + (h * 2)...

...(pNv->dev->chipset >= 0x110) { > + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); > + PUSH_DATA (push, 256); > + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32); No PUSH_DATAh in the DDX? > + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA)); > + BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1); > + PUSH_DATA (push, 0x80); > + > + PUSH_DATAf(push, dx); > + PUSH_DATAf(push, dy + (h * 2)); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, sx); > + PUSH_DATAf(push, sy + (h * 2)); > + PUSH_DATA...

...#12 0x00007fe0a48a4b4e in nouveau_pushbuf_space (push=push at entry=0x564e651158c0, dwords=dwords at entry=26, relocs=relocs at entry=0, pushes=<optimized out>, pushes at entry=0) at pushbuf.c:689 #13 0x00007fe0a50d05b6 in PUSH_SPACE (size=26, push=0x564e651158c0) at ./nouveau_winsys.h:31 #14 BEGIN_1IC0 (size=17, mthd=9100, subc=0, push=0x564e651158c0) at ./nvc0/nvc0_winsys.h:134 #15 nve4_update_surface_bindings (nvc0=0x564e66cb5750) at nvc0/nvc0_tex.c:1281 #16 nvc0_validate_surfaces (nvc0=0x564e66cb5750) at nvc0/nvc0_tex.c:1309 #17 0x00007fe0a50c78bc in nvc0_state_validate (nvc0=nvc0 at entry=0x5...

The headers hadn't been regenerated in a long time, and there were a few minor divergences. Among other things, rnndb has changed naming to G80/etc, for now I've not tackled switching that over and manually replaced the nvidia codenames back to the chip ids. However no other modifications of the headergen'd headers was done. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

I believe I've addressed all the feedback from the first time around, and also made fixes necessary for GM20x based on testing results. I believe now it should actually work for all GM10x and GM20x. Further, GP10x should be very easy to add, but without someone to actually test I didn't want to claim support for it. Ilia Mirkin (7): exa: add GM10x acceleration support hwdefs: update