Displaying 4 results from an estimated 4 matches for "bclr64".
2016 Nov 03
2
rotl: undocumented LLVM instruction?
Is there any way to get it to delay this optimization where it goes from
this:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, C...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...rmer did in the earlier stage.
>
> Phil
>
> On Thu, Nov 3, 2016 at 2:07 PM, Phil Tomson <phil.a.tomson at gmail.com>
> wrote:
>
>> Is there any way to get it to delay this optimization where it goes from
>> this:
>>
>> Initial selection DAG: BB#0 'bclr64:entry'
>> SelectionDAG has 14 nodes:
>> t0: ch = EntryToken
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = s...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...2016 at 2:07 PM, Phil Tomson
> <phil.a.tomson at gmail.com <mailto:phil.a.tomson at gmail.com>> wrote:
>
> Is there any way to get it to delay this optimization where
> it goes from this:
>
> Initial selection DAG: BB#0 'bclr64:entry'
> SelectionDAG has 14 nodes:
> t0: ch = EntryToken
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
> t6: i64 = sub t4, Constant:i...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one
of our code generation tests is breaking in 3.9.
The test is:
; RUN: llc < %s -march=xstg | FileCheck %s
define i64 @bclr64(i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK: bclr r1, r0, r1, 64
%sub = sub i64 %b, 1
%shl = shl i64 1, %sub
%xor = xor i64 %shl, -1
%and = and i64 %a, %xor
ret i64 %and
}
I ran llc with -debug to get a better idea of what's going on and found:
Initial selection DAG: BB#0...