Displaying 9 results from an estimated 9 matches for "bclr".
2016 Nov 03
2
rotl: undocumented LLVM instruction?
Is there any way to get it to delay this optimization where it goes from
this:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7,...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...2016 at 2:07 PM, Phil Tomson
> <phil.a.tomson at gmail.com <mailto:phil.a.tomson at gmail.com>> wrote:
>
> Is there any way to get it to delay this optimization where
> it goes from this:
>
> Initial selection DAG: BB#0 'bclr64:entry'
> SelectionDAG has 14 nodes:
> t0: ch = EntryToken
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
> t6: i64 = sub t4, Constant...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...rmer did in the earlier stage.
>
> Phil
>
> On Thu, Nov 3, 2016 at 2:07 PM, Phil Tomson <phil.a.tomson at gmail.com>
> wrote:
>
>> Is there any way to get it to delay this optimization where it goes from
>> this:
>>
>> Initial selection DAG: BB#0 'bclr64:entry'
>> SelectionDAG has 14 nodes:
>> t0: ch = EntryToken
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 =...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one
of our code generation tests is breaking in 3.9.
The test is:
; RUN: llc < %s -march=xstg | FileCheck %s
define i64 @bclr64(i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK: bclr r1, r0, r1, 64
%sub = sub i64 %b, 1
%shl = shl i64 1, %sub
%xor = xor i64 %shl, -1
%and = and i64 %a, %xor
ret i64 %and
}
I ran llc with -debug to get a better idea of what's going on and found:
Initial selection DAG: BB...
2016 Jun 04
4
Gluing arbitrary nodes together
...ustom lowering hook to convert ISD::ATOMIC_LOAD into a standard
ISD::LOAD with the save/restore/interrupt nodes glued to it.
Here’s what I have so far:
// Store `SREG`
auto Save = DAG.getCopyFromReg(DAG.getEntryNode(), DL, AVR::SREG, MVT::i8);
// Disable interrupts (`clr` is equivalent to `bclr 7`).
auto ClearInterrupts = DAG.getNode(AVRISD::BCLR, DL, MVT::Glue,
DAG.getConstant(7, DL, MVT::i8));
// Perform the nonatomic load.
auto *Node = cast<AtomicSDNode>(AtomicOp.getNode());
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp),
AtomicOp.getValueType(),...
2013 Apr 10
3
[LLVMdev] If Conversion and predicated returns
...t; = LI 0
%CR0<def> = CMPLWI %R3, 0
BCC 68, %CR0, <BB#3>
Successors according to CFG: BB#3(16) BB#1(16)
BB#1: derived from LLVM BB %while.body.lr.ph
Live Ins: %R3
Predecessors according to CFG: BB#0
%CR0<def> = CMPLWI %R3<kill>, 0
BCLR 68, %CR0, %LR<imp-use>, %RM<imp-use>
Successors according to CFG: BB#3(16) BB#2(16)
BB#2: derived from LLVM BB %while.body
Predecessors according to CFG: BB#2 BB#1
B <BB#2>
Successors according to CFG: BB#2
BB#3: derived from LLVM BB %while.end
Predecesso...
2014 Aug 17
0
[PATCH 09/10] pwr/fuc: make $r1-$r10 registers callee-saved in kernel.fuc
...r14)
@@ -126,6 +132,8 @@ wait:
cmp b32 $r9 $r11
bra l #wait_loop
wait_done:
+ pop $r8
+ pop $r9
ret
// $r15 - current (kern)
@@ -460,6 +468,9 @@ send:
// $r14 - process
// $r0 - zero
recv:
+ push $r9
+ push $r8
+
ld b32 $r8 D[$r14 + #proc_qget]
ld b32 $r9 D[$r14 + #proc_qput]
bclr $flags $p1
@@ -492,6 +503,8 @@ recv:
bset $flags $p1
pop $r15
recv_done:
+ pop $r8
+ pop $r9
ret
init:
diff --git a/nvkm/subdev/pwr/fuc/nv108.fuc.h b/nvkm/subdev/pwr/fuc/nv108.fuc.h
index fe8dd23..82d6bbc 100644
--- a/nvkm/subdev/pwr/fuc/nv108.fuc.h
+++ b/nvkm/subdev/pwr/fuc/nv108.fuc....
2016 Mar 10
0
[PATCH] gr/fuc: Store $r0 in interrupt handler
...c
index e168b83..dc60509 100644
--- a/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
+++ b/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
@@ -322,6 +322,7 @@ main:
// interrupt handler
ih:
+ push $r0
push $r8
mov $r8 $flags
push $r8
@@ -358,6 +359,7 @@ ih:
pop $r8
mov $flags $r8
pop $r8
+ pop $r0
bclr $flags $p0
iret
diff --git a/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h b/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
index 231f696..5f4ddfe 100644
--- a/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
+++ b/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
@@ -382,56 +382,57 @@ uint32_t gf1...
2014 Aug 17
9
[PATCH 01/10] bios/fan: add support for maxwell's fan management table v2
Re-use the therm-exported fan structure with only two minor modifications:
- pwm_freq: u16 -> u32;
- add fan_type (toggle or PWM)
v2:
- Do not memset the table to 0 as it erases the pre-set default values
Signed-off-by: Martin Peres <martin.peres at free.fr>
---
drm/Kbuild | 1 +
drm/core/include/subdev/bios/fan.h | 1 +
drm/core/subdev/bios/fan.c | 1