search for: bclk

...but somehow registers matching default values aren't re-written. I'm not sure where, (ALSA?) issues a chip software reset and then only programs the needed registers skipping one of the 2 registers for the PLL that generates the sampling clock. This results in the PLL generating a 1.5MHz BCLK/46.875KHz frame clock and not the desired 1.536MHz/48KHz clocks. So the resulting audio stream is short in samples over time every second. Now I just need to determine why/where the layer that's not writing BOTH PLL_D registers and fix it. Yay. But I thought I'd let you guys know this b...

Hi all, New to list and Opus Codec. I've been using it on a beagleboneblack with 'arecord'. One of the things I've noticed while encoding is that Opus reports a float with an 'x' along with "realtime". Where can I look up where this calculation is derived? It got me looking and I've noticed that when I record something from a known source (in testing)