Displaying 3 results from an estimated 3 matches for "bc_v2i64".
2009 Mar 24
2
[LLVMdev] Reducing .td redundancy
...VR128:
$src2))]>;
// Bitconverted vector operation
def PSrm : PSI<opc, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
(memopv2i64 addr:$src2)))]>;
// ...
}
defm AND : ...
defm OR : ...
I suspect we could get rid of a lot of redundancy if SOME_CONCAT could really
work. I've run into a few places where I think something like this could be
used....
2009 Mar 24
0
[LLVMdev] Reducing .td redundancy
...tconverted vector operation
> def PSrm : PSI<opc, MRMSrcMem,
> (outs VR128:$dst), (ins VR128:$src1, f128mem:
> $src2),
> !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst,
> $src2}"),
> [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32
> VR128:$src1)),
> (memopv2i64 addr:$src2)))]>;
> // ...
> }
>
> defm AND : ...
> defm OR : ...
>
> I suspect we could get rid of a lot of redundancy if SOME_CONCAT
> could really
> work. I've run into a few p...
2009 Apr 30
6
[LLVMdev] RFC: AVX Pattern Specification [LONG]
...PSrr : PSI<0x55, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
"andnps\t{$src2, $dst|$dst, $src2}",
[(set VR128:$dst,
(v2i64 (and (xor VR128:$src1,
(bc_v2i64 (v4i32 immAllOnesV))),
VR128:$src2)))]>;
SSE2 :
def ANDNPDrr : PDI<0x55, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
"andnpd\t{$src2, $dst|$dst, $src2}",
[(set VR128:$...