Displaying 14 results from an estimated 14 matches for "bbaa".
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2008 Nov 30
6
Regex: workaround for variable length negative lookbehind
Hi all
I have the following regular expression problem: I want to find
complete elements of a vector that end in a repeated character but
where the repetition doesn't make up the whole word. That is, for the
vector vec:
vec<-c("aaaa", "baaa", "bbaa", "bbba", "baamm", "aa")
I would like to get
"baaa"
"bbaa"
"baamm"
>From tools where negative lookbehind can involve variable lengths, one
would think this would work:
grep("(?<!(?:\\1|^))(.)\\1{1,}$", vec, perl=T)...
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...total 96-bit in 'one' register.
You can store a 24-bit integer or a s7.16 floating-point data into each
channel.
You can name each channel 'a', 'b', 'c', 'd'.
Here is an example of the operation in this H/W platform:
ADD R3.ab, R1.abab, R2.bbaa
it means
Add 'abab' channel of R1 and 'bbaa' channel of R2, and put the
result into the 'ab' channel of R3.
It's complicate.
Imagine a non-existed temp register named 'Rt1', the content of its
'a','b','c','d' channel...
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...tore a 24-bit integer or a s7.16 floating-point data into
> > each channel.
> > You can name each channel 'a', 'b', 'c', 'd'.
>
> > Here is an example of the operation in this H/W platform:
>
> > ADD R3.ab, R1.abab, R2.bbaa
>
> > it means
>
> > Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> > put the result into the 'ab' channel of R3.
>
> > It's complicate.
> > Imagine a non-existed temp register named 'Rt1', the content...
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...ster.
> You can store a 24-bit integer or a s7.16 floating-point data into
> each channel.
> You can name each channel 'a', 'b', 'c', 'd'.
>
> Here is an example of the operation in this H/W platform:
>
> ADD R3.ab, R1.abab, R2.bbaa
>
> it means
>
> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> put the result into the 'ab' channel of R3.
>
> It's complicate.
> Imagine a non-existed temp register named 'Rt1', the content of its
> 'a'...
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...ger or a s7.16 floating-point data into
>>> each channel.
>>> You can name each channel 'a', 'b', 'c', 'd'.
>>
>>> Here is an example of the operation in this H/W platform:
>>
>>> ADD R3.ab, R1.abab, R2.bbaa
>>
>>> it means
>>
>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>> put the result into the 'ab' channel of R3.
>>
>>> It's complicate.
>>> Imagine a non-existed temp register named &...
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...ger or a s7.16 floating-point data into
>>> each channel.
>>> You can name each channel 'a', 'b', 'c', 'd'.
>>
>>> Here is an example of the operation in this H/W platform:
>>
>>> ADD R3.ab, R1.abab, R2.bbaa
>>
>>> it means
>>
>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>> put the result into the 'ab' channel of R3.
>>
>>> It's complicate.
>>> Imagine a non-existed temp register named &...
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...16 floating-point data into
> >>> each channel.
> >>> You can name each channel 'a', 'b', 'c', 'd'.
>
> >>> Here is an example of the operation in this H/W platform:
>
> >>> ADD R3.ab, R1.abab, R2.bbaa
>
> >>> it means
>
> >>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> >>> put the result into the 'ab' channel of R3.
>
> >>> It's complicate.
> >>> Imagine a non-existed temp reg...
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...16 floating-point data into
> >>> each channel.
> >>> You can name each channel 'a', 'b', 'c', 'd'.
>
> >>> Here is an example of the operation in this H/W platform:
>
> >>> ADD R3.ab, R1.abab, R2.bbaa
>
> >>> it means
>
> >>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> >>> put the result into the 'ab' channel of R3.
>
> >>> It's complicate.
> >>> Imagine a non-existed temp reg...
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...ta into
>>>>> each channel.
>>>>> You can name each channel 'a', 'b', 'c', 'd'.
>>
>>>>> Here is an example of the operation in this H/W platform:
>>
>>>>> ADD R3.ab, R1.abab, R2.bbaa
>>
>>>>> it means
>>
>>>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>>>> put the result into the 'ab' channel of R3.
>>
>>>>> It's complicate.
>>>>> Ima...
2017 Jul 19
2
[ovirt-users] ovirt 4.1 hosted engine hyper converged on glusterfs 3.8.10 : "engine" storage domain alway complain about "unsynced" elements
...-403e-ad51-f56d9ca5d7a7.20
> /__DIRECT_IO_TEST__
> Status: Connected
> Number of entries: 12
>
> Brick node02:/gluster/engine/brick
> /8f215dd2-8531-4a4f-b6ed-ea789dd8821b/images/19d71267-
> 52a4-42a3-bb1e-e3145361c0c2/7a215635-02f3-47db-80db-8b689c6a8f01
> <gfid:9a601373-bbaa-44d8-b396-f0b9b12c026f>
> /8f215dd2-8531-4a4f-b6ed-ea789dd8821b/dom_md/ids
> <gfid:1e309376-c62e-424f-9857-f9a0c3a729bf>
> <gfid:e3565b50-1495-4e5b-ae88-3bceca47b7d9>
> <gfid:4e33ac33-dddb-4e29-b4a3-51770b81166a>
> /__DIRECT_IO_TEST__
> <gfid:67606789-1f34-...
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...ta into
>>>>> each channel.
>>>>> You can name each channel 'a', 'b', 'c', 'd'.
>>
>>>>> Here is an example of the operation in this H/W platform:
>>
>>>>> ADD R3.ab, R1.abab, R2.bbaa
>>
>>>>> it means
>>
>>>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>>>> put the result into the 'ab' channel of R3.
>>
>>>>> It's complicate.
>>>>> Ima...
2008 Nov 24
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...>>>>> each channel.
> >>>>> You can name each channel 'a', 'b', 'c', 'd'.
>
> >>>>> Here is an example of the operation in this H/W platform:
>
> >>>>> ADD R3.ab, R1.abab, R2.bbaa
>
> >>>>> it means
>
> >>>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> >>>>> put the result into the 'ab' channel of R3.
>
> >>>>> It's complicate.
> >>>...
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...> each channel.
>>>>>>> You can name each channel 'a', 'b', 'c', 'd'.
>>
>>>>>>> Here is an example of the operation in this H/W platform:
>>
>>>>>>> ADD R3.ab, R1.abab, R2.bbaa
>>
>>>>>>> it means
>>
>>>>>>> Add 'abab' channel of R1 and 'bbaa' channel of R2,
>>>>>>> and
>>>>>>> put the result into the 'ab' channel of R3.
>>
>>>...
2017 Jul 19
0
[ovirt-users] ovirt 4.1 hosted engine hyper converged on glusterfs 3.8.10 : "engine" storage domain alway complain about "unsynced" elements
...5d7a7.20
> /__DIRECT_IO_TEST__
> Status: Connected
> Number of entries: 12
>
> Brick node02:/gluster/engine/brick
> /8f215dd2-8531-4a4f-b6ed-ea789dd8821b/images/19d71267-52a4-42a3-bb1e-e3145361c0c2/7a215635-02f3-47db-80db-8b689c6a8f01
> <gfid:9a601373-bbaa-44d8-b396-f0b9b12c026f>
> /8f215dd2-8531-4a4f-b6ed-ea789dd8821b/dom_md/ids
> <gfid:1e309376-c62e-424f-9857-f9a0c3a729bf>
> <gfid:e3565b50-1495-4e5b-ae88-3bceca47b7d9>
> <gfid:4e33ac33-dddb-4e29-b4a3-51770b81166a>
> /__DIRECT_IO_TEST__
>...