search for: bb6

Displaying 20 results from an estimated 46 matches for "bb6".

Did you mean: b6
2016 May 05
2
No remapping of clone instruction in CloneBasicBlock
Hi, Found CloneBasicBlock utility only does the cloning without any remapping. Consider below example: Input block: sw.epilog: ; preds = %sw.bb20, %sw.bb15, %sw.bb10, %sw.bb6, %sw.bb2, %sw.bb, %while.body, %if.end29 %no_final.1 = phi i32 [ %no_final.055, %while.body ], [ 1, %if.end29 ], [ %no_final.055, %sw.bb20 ], [ %no_final.055, %sw.bb15 ], [ %no_final.055, %sw.bb10 ], [ %no_final.055, %sw.bb6 ], [ %no_final.055, %sw.bb2 ], [ %no_final.055, %sw.bb ] %locinput.1 =...
2011 Dec 09
1
[LLVMdev] Branch Instruction layout
Given an instruction like this: br i1 %tmp12, label %bb5, label %bb6 I'm confused as to why Operand(1) = bb6 and not bb5 and why Operand(2) is bb5 and not bb6. Why in the instruction does the true path always list first but when accessing the operands of the instruction, it is backwards? Is there a particular reason for this? -------------- next part ---------...
2005 Apr 22
0
'Not listening for calling name'
...em I would appreciate some help. One of the main errors I am getting from the logs from the windows clients is this: smbd/password.c:(1558) domain_client_validate: could not fetch trust account password for domain DOMAIN. And the errors that I am getting when I try to do an smbclient //bb6/user -d 6 is the following: added interface ip=xxx.xxx.xxx.xxx bcast=xxx.xxx.xxx.255 nmask=255.255.255.0 added interface ip=192.168.2.4 bcast=192.168.2.255 nmask=255.255.255.0 Client started (version 2.2.0). resolve_lmhosts: Attempting lmhosts lookup for name bb6<0x20> startlmhosts: C...
2008 Jul 12
3
[LLVMdev] Little bug in LoopInfo after Rotate?
....next, 16 ; <i1> [#uses=1] br i1 %exitcond, label %bb3, label %bb1 bb3: ; preds = %bb1 %indvar.next9 = add i32 %i.0.reg2mem.0.ph, 1 ; <i32> [#uses=2] %exitcond10 = icmp eq i32 %indvar.next9, 32 ; <i1> [#uses=1] br i1 %exitcond10, label %bb6, label %bb1 bb6: ; preds = %bb3 ret i32 0 } LoopInfo says: Loop Containing: %bb1, %bb3. Only detects the outer loop By the way, if I separate the header of the outer loop, like: define i32 @f() nounwind { entry: br label %bb0 bb0: ; preds = %entry, %bb3 %i.0.reg2mem...
2016 Sep 21
2
Propagation of debug information for variable into basic blocks.
...e. > I had to construct an example to see the problem, but my example is bit contrived (it depends on starting in the middle of the graph) so I wonder if there is a better counterexample. BB0:y BB1:x,y | | BB2:⊥ BB3:⊥ BB4:⊥ | / | / BB5:x | / \ | / BB6: ? | +-> back-edge to BB1, BB4 BB5 has a definition for x but neither kills nor defines y. No block ever kills y. Let's assume we for whatever reason started in BB5. The first join() at BB6 will yield the set [x] (BB3 and BB4 are unvisited and thus skipped, just as if they...
2011 Nov 21
1
[LLVMdev] Fwd: Order of Basic Blocks
...m> This worked, though the RPO_iterator apparently wasn't what I was looking for anyways, it seems it doesn't rreally go top->down. I have a simple example code, where the block follow this path: BB0->BB1 (T), BB8 (F) BB1-> BB2 (T), BB3 (F) BB2-> BB4 BB3-> BB5 BB4-> BB6 BB5-> BB8 (T), BB5 (F) BB6-> BB7 (T), BB4 (F) BB7-> BB8 (T), BB4 (F) BB8 (end) So, this is the basic block flow graph. When I iterate using the ReversePostOrderTraversal iterator, the basic blocks vistied are in this order: BB0, BB1, BB3, BB2, BB7, BB6, BB4, BB5, BB8 Can someone explain...
2007 Aug 08
1
[LLVMdev] CFG leaf node
...%entry %indvar = phi uint [ 0, %entry ], [ %indvar.next, %bb ] ; <uint> [#uses=2] %indvar.next = add uint %indvar, 1 ; <uint> [#uses=2] %exitcond = seteq uint %indvar.next, 25 ; <bool> [#uses=1] br bool %exitcond, label %bb6, label %bb bb6: ; preds = %bb %n.0.0 = cast uint %indvar to int ; <int> [#uses=1] %k_addr.0.0 = add int %n.0.0, %k ; <int> [#uses=1] %tmp1 = add int %k_addr.0.0, 1 ; <int> [#uses=1] ret int %tmp1 } -...
2010 Oct 28
3
[LLVMdev] Landing my new development on the trunk ...
...of infrastructure for loop > passes; why does this pass have its own code for finding loops? I saw the loop infrastructure for CFG loops. This algorithm finds loops in the data flow (more precisely: strongly-connected components in the SSA-graph), e.g. bb5: %20 = add nsw i32 %i.0, 1 br label %bb6 bb6: %i.0 = phi i32 [ 0, %entry ], [ %20, %bb5 ] There is a data flow loop between %20 and %i.0. The OSR paper has a nice figure showing data flow loops. Here is small excerpt from the OSR paper: "OSR is driven by a simple depth-first search of the SSA-graph, using Tarjan’s strongly-conn...
2010 Oct 07
2
[LLVMdev] [Q] x86 peephole deficiency
...r=BB0_1 Depth=1 cmpl $2, %edi je .LBB0_6 # BB#3: # %nz.non-middle # in Loop: Header=BB0_1 Depth=1 cmpl $2, %edi jbe .LBB0_4 # BB#5: # %sw.bb6 ret the second 'cmpl' is totally redundant, which pass is (or would be) in charge of removing it? Cheers, Gabor
2011 Jul 06
0
[LLVMdev] code generation removes duplicated instructions
On 6 July 2011 14:55, D S Khudia <daya.khudia at gmail.com> wrote: > The following is an example code generation for arm and x86 for a same IR > BB. In the x86 code I can see that the same computation is done twice and > result is stored in two different registers and then these two different > registers are used for comparision. Yes, but you shouldn't rely on it, since the
2010 Oct 28
0
[LLVMdev] Landing my new development on the trunk ...
...s; why does this pass have its own code for finding loops? > > I saw the loop infrastructure for CFG loops. This algorithm finds loops in > the data flow (more precisely: strongly-connected components in the > SSA-graph), e.g. > > bb5: > %20 = add nsw i32 %i.0, 1 > br label %bb6 > > bb6: > %i.0 = phi i32 [ 0, %entry ], [ %20, %bb5 ] > > There is a data flow loop between %20 and %i.0. The OSR paper has a nice > figure showing data flow loops. > > Here is small excerpt from the OSR paper: > > "OSR is driven by a simple depth-first search of...
2010 Aug 05
3
[LLVMdev] a problem when using postDominatorTree
...real applications, the > following error occurs: > /Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries. > [1] <<exit node>> {0,21} > [2] %bb1 {1,2} > [2] %bb {3,4} > [2] %entry {5,6} > [2] %bb8 {7,20} > [3] %bb7 {8,9} > [3] %bb2 {10,11} > [3] %bb6 {12,13} > [3] %bb5 {14,19} > [4] %bb4 {15,16} > [4] %bb3 {17,18} > 0 opt 0x085643e8 > Stack dump: > 0. Program arguments: opt > -load=/home/a_i/llvm/llvm-2.7/Release/lib/ConsDumper.so -consdumper -f > -o pbzip2_2s.bc pbzip2.bc -debug > 1. Running pass 'dump constrai...
2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
...n detected as part of OrigLI. @1520 identity COPY 122 to 122 ... BB4: ... BB5: @1764 // This is where vreg111 is split and tracing of vreg121 begins. OrigVNI passed is @1520. // Exits with two edges into two one-block loops, with one exit block each, which are joined in BB12. // Succs BB6, BB8 BB6: {} // Single block nested loop BB7: // pred BB6, succ BB12 @2948 sibling COPY 121 to 122 BB8: // pred BB5 {} // Single block nested loop BB9: // pred BB8, succ BB12 @2968 sibling COPY 121 to 122 BB12: // joining BB7 and BB9 phi 9 BB13: // Latch block for outer loop, has edge...
2011 Jul 06
2
[LLVMdev] code generation removes duplicated instructions
Thank you for replying. Yes. The remaining part of the BB is in splitted basic block. The following is an example code generation for arm and x86 for a same IR BB. In the x86 code I can see that the same computation is done twice and result is stored in two different registers and then these two different registers are used for comparision. By the way I am duplicating instruction and inserting
2016 Sep 21
2
Propagation of debug information for variable into basic blocks.
> > > Conceptually, the LiveDebugValues data flow analysis should be using > three-valued logic arranged in a lattice > > ⊥ (uninitialized / don't know) > / \ > true false (is (not) available) > > where join(x, ⊥) = x, otherwise it behaves like boolean &. > > All debug variable values are initialized to the bottom element first. > After
2011 Jul 06
2
[LLVMdev] code generation removes duplicated instructions
...lc. Since I am inserting a new basic block (contains printf statement and program exit) which is jumped upon based on the result of the comparison, the compiler cannot/shouldnot optimize that away by means of DCE or anything else. The same kind of stuff is happening for the following duplication. bb6.split: ; preds = %bb6 %33 = load i32* %32, align 4 %34 = load i32* %i, align 4 %HV4_3 = sub nsw i32 %34, %33 %35 = sub nsw i32 %34, %33 %HV4_2 = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %HV4_3 %36 = getelementptr inbounds [100 x i32]* %a,...
2016 Feb 08
2
LoopIdiomRegognize vs Preserved
Hi, I'm having problems with the LoopIdiomRegognizer crashing on me with An asserting value handle still pointed to this value! UNREACHABLE executed at ../lib/IR/Value.cpp:695! If I remove AU.addPreserved<LoopInfoWrapperPass>(); or AU.addPreserved<AAResultsWrapperPass>(); everything goes well. The C-code triggering this is void foo(int a[10][10]) { int i, j,
2010 Oct 07
0
[LLVMdev] [Q] x86 peephole deficiency
...$2, %edi > je .LBB0_6 > # BB#3: # %nz.non-middle > # in Loop: Header=BB0_1 > Depth=1 > cmpl $2, %edi > jbe .LBB0_4 > # BB#5: # %sw.bb6 > ret > > the second 'cmpl' is totally redundant, which pass is > (or would be) in charge of removing it? MachineCSE should be in charge of zapping it. -Chris
2013 Oct 10
2
[LLVMdev] Are there implicit rules or conventions for an llvm frontend to generate llvm IR?
...orming? 2. Is it possible for a frontend to generate a function whose CFG is something like: bb0 / \ bb1 bb2 / \ / \ bb3 bb4 bb5 \ | / \ | / \ | / bb6 (In this case, if I understand correctly, bb4 is control dependent on both bb1 and bb2.) I think it at least possible in theory, and there is a simple case: int foo(int i) { if (i < 0) { if (i % 2 == 0) { i += 1; } else { i += 2; } } else { if (i % 2 == 0) {...
2009 Apr 28
3
[LLVMdev] how to resolve llvm exception IR?
...tream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(%"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([10 x i8]* @.str, i32 0, i32 0)) 60 to label %bb6 unwind label %lpad10 ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=0] 61 62 bb6: ; preds = %bb 63 tail call void @__cxa_end_catch() 64 ret i32 0 65 66 lpad: ; preds = %entr...