Displaying 20 results from an estimated 90 matches for "bb4".
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2010 Jun 29
0
[LLVMdev] Confuse on getSCEVAtScope
On Jun 29, 2010, at 7:08 AM, ether zhhb wrote:
>
> why computeSCEVAtScope not try to get the operands in the current
> scope like the function do with SCEVCommutativeExpr, like:
>
> if (const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(V)) {
> if (!L || !AddRec->getLoop()->contains(L)) {
> ...
> // Then, evaluate the AddRec.
>
2010 Jun 29
2
[LLVMdev] Confuse on getSCEVAtScope
hi all,
i have SCEVAddRec
{{(32 + @edge.8265),+,32}<Loop0>,+,4}<Loop1>
where Loop0 and Loop1 are brothers (loops at the same level of the
loopnest), and Loop0 have a computable backedge taken count.
when i call getSCEVAtScope({{(32 +
@edge.8265),+,32}<Loop0>,+,4}<Loop1> , Loop1), it just give me a
{{(32 + @edge.8265),+,32}<Loop0>,+,4}<Loop1>,
instead of
2020 May 03
0
International Conference on Marketing and Technologies (ICMarkTech'20), Lisbon, Portugal
...----- ------------------------------ ------------------------------ --------------------------
Call For Papers
ICMarkTech'20 - International Conference on Marketing and Technologies of 2020
8 to 10 October 2020 in Lisbon, Portugal
http://www.icmarktech.org <http://mkt.icsporto.com/go/bb4-7ad1e005744-35a9050fc2c-f010a2aaf9dd4e908dd79a41e1e1QKnehstweseR>
------------------------------ ------------------------------ ------------------------------ ------------------------------ ------------------------------ -------------------------
Scope
ICMarkTech'20 <htt...
2011 Jan 25
2
[LLVMdev] Update PHINode after extracting code
Hi all,
I have problem with ExtractCodeRegion (CodeExtractor.cpp).
My original program is as follows.
bb:
...
%tmp.15 = load %struct.MYSQL_ROWS** %3, align 4
...
bb1:
...
%tmp.1 = load %struct.MYSQL_ROWS** %6, align 4
...
bb4: ; preds = %bb1, %bb,
%entry
%tmp.0 = phi %struct.MYSQL_ROWS* [ null, %entry ], [ %tmp.15, %bb ], [
%tmp.1, %bb1 ]
%tmp.0 is the PHINode whose value is from entry, bb and bb1.
After extracting bb and bb1 into new function, the program becomes
codeRep...
2016 Sep 21
2
Propagation of debug information for variable into basic blocks.
...> How to achieve this for real is ... not obvious at a glance.
>
I had to construct an example to see the problem, but my example is bit contrived (it depends on starting in the middle of the graph) so I wonder if there is a better counterexample.
BB0:y BB1:x,y
| |
BB2:⊥ BB3:⊥ BB4:⊥
| / | /
BB5:x | /
\ | /
BB6: ?
|
+-> back-edge to BB1, BB4
BB5 has a definition for x but neither kills nor defines y. No block ever kills y. Let's assume we for whatever reason started in BB5. The first join() at BB6 will yield the set...
2010 Nov 17
1
[LLVMdev] Copy Instruction from one Basic block to another
.../ \
bb1 bb2
\ /
bb3
|
bb4
Now I want to create a new basic block, say bb5 between bb2 &
bb3, copy some instructions from bb3 to bb5. Then I want to add between bb2
and bb3, then outgoing edge from bb5 is to be attached with bb4. Finally my
program will look like :...
2012 Jul 25
2
[LLVMdev] Question about an unusual jump instruction
...= COPY %R0; // R0 contains 'a'
J <#BB1>
BB1:
%vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3>
J <#BB2>
BB2:
// loop body
BB3:
%vreg3<def> = ADDI %vreg1<kill>, 1
CMPNE %vreg3, 0, %SR<implicit,def>
JNZ <#BB1>
J <#BB4>
BB4:
// end
With the optimization pass I replace the decrement, comparison and conditional
jump with the DECJNZ. The resulting code will be:
BB0:
%vreg0<def> = COPY %R0; // R0 contains 'a'
J <#BB1>
BB1:
%vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <...
2011 Nov 21
1
[LLVMdev] Fwd: Order of Basic Blocks
...benny.kra at googlemail.com>
This worked, though the RPO_iterator apparently wasn't what I was looking
for anyways, it seems it doesn't rreally go top->down.
I have a simple example code, where the block follow this path:
BB0->BB1 (T), BB8 (F)
BB1-> BB2 (T), BB3 (F)
BB2-> BB4
BB3-> BB5
BB4-> BB6
BB5-> BB8 (T), BB5 (F)
BB6-> BB7 (T), BB4 (F)
BB7-> BB8 (T), BB4 (F)
BB8 (end)
So, this is the basic block flow graph. When I iterate using the
ReversePostOrderTraversal iterator, the basic blocks vistied are in this
order:
BB0, BB1, BB3, BB2, BB7, BB6, BB4, BB5...
2009 May 08
2
[LLVMdev] Splitting a basic block, replacing it's terminator
...bb);
That seems to work, but later passes are dieing. When I dump the
function from my debugger, I notice that the new block (the second
half of the block I split) has a "<null operand>" as a predecessor.
What am I doing wrong?
Here's what bb->getParent()->dump shows. bb4.preheader is the
original basic block; bb4.preheader.noExit is the block created by the
splitBasicBlock() operation:
bb4.preheader: ; preds = %bb5, %preheader
; blah blah blah
%6 = icmp slt i32 %timestamp, 0 ; <i1> [#uses=1]
br i1 %6, label %__mtcg_sync...
2011 Feb 04
3
[LLVMdev] Data layout of structs
...i8* %4 to %struct.item** ; <%struct.item**> [#uses=1]
store %struct.item* %head.07, %struct.item** %5, align 8
%tmp = add i32 %indvar, 2 ; <i32> [#uses=1]
%6 = icmp sgt i32 %tmp, %length ; <i1> [#uses=1]
br i1 %6, label %bb4.preheader, label %bb
bb4.preheader: ; preds = %bb
%7 = icmp eq %struct.item* %2, null ; <i1> [#uses=1]
br i1 %7, label %return, label %bb3
bb3: ; preds = %bb3, %bb4.preheader
%curr.06 = phi...
2012 Jul 25
0
[LLVMdev] Question about an unusual jump instruction
...B1>
> BB1:
> %vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3>
> J <#BB2>
> BB2:
> // loop body
> BB3:
> %vreg3<def> = ADDI %vreg1<kill>, 1
> CMPNE %vreg3, 0, %SR<implicit,def>
> JNZ <#BB1>
> J <#BB4>
> BB4:
> // end
>
> With the optimization pass I replace the decrement, comparison and conditional
> jump with the DECJNZ. The resulting code will be:
>
> BB0:
> %vreg0<def> = COPY %R0; // R0 contains 'a'
> J <#BB1>
> BB1:
> %vreg...
2015 Mar 24
2
[LLVMdev] RFC - Improvements to PGO profile support
Example. Assuming the cap is 'C'
void bar()
{
// ENTRY count is 4*C, after capping it becomes 'C'
...
}
void test()
{
// BB1: count(BB1) = C
bar();
// BB2: count(BB2) = C
bar();
}
void test2()
{
// BB3: count(BB3) = C
bar();
// BB4: count(BB4) = C
bar();
}
What would inliner see here ? When it sees callsite1 -- it might mistaken
that is the only dominating callsite to 'bar'.
David
On Tue, Mar 24, 2015 at 12:57 PM, Chandler Carruth <chandlerc at google.com>
wrote:
>
> On Tue, Mar 24, 2015 at 12:53...
2010 Jun 24
2
[LLVMdev] How to prevent an instruction to be executed more than once?
I need to mark the beginning of some regions of code, that I want to patch at
runtime.
In this case, I want to mark the beginning of BB4 and then to patch the
jumps, because I want to temporarily change the flow at runtime and then to
restore the previous version.
In order to patch, I need to know the exact structure of the generated code.
So, I might have a BasicBlock like:
BB4:
call void asm "label_BB4:\0A", "&qu...
2017 Oct 27
6
RFC: We need to explicitly state that some functions are reserved by LLVM
...tic bug report. Consider the LLVM IR:
target triple = "x86_64-unknown-linux-gnu"
define internal i8* @access({ i8* }* %arg, i64) {
ret i8* undef
}
define i8* @g({ i8* }* %arg) {
bb:
%tmp = alloca { i8* }*, align 8
store { i8* }* %arg, { i8* }** %tmp, align 8
br i1 undef, label %bb4, label %bb1
bb1:
%tmp2 = load { i8* }*, { i8* }** %tmp, align 8
%tmp3 = call i8* @access({ i8* }* %tmp2, i64 undef)
br label %bb4
bb4:
ret i8* undef
}
This IR, if compiled with `opt -passes='cgscc(inline,argpromotion)'
-disable-output` hits a bunch of asserts in the LazyCallGraph...
2011 Jan 27
0
[LLVMdev] Update PHINode after extracting code
...ote:
> Hi all,
> I have problem with ExtractCodeRegion (CodeExtractor.cpp).
> My original program is as follows.
> bb:
> ...
> %tmp.15 = load %struct.MYSQL_ROWS** %3, align 4
> ...
> bb1:
> ...
> %tmp.1 = load %struct.MYSQL_ROWS** %6, align 4
> ...
> bb4: ; preds = %bb1, %bb,
> %entry
> %tmp.0 = phi %struct.MYSQL_ROWS* [ null, %entry ], [ %tmp.15, %bb ], [
> %tmp.1, %bb1 ]
>
> %tmp.0 is the PHINode whose value is from entry, bb and bb1.
> After extracting bb and bb1 into new function,...
2010 Aug 12
0
[LLVMdev] Questions about trip count
...gv) {
int i = 0;
for (; i < 4; i++) {
int j = 0;
for (; j < 8; j++) {
printf("%c\n", argv[i][j]);
}
}
}
It prints the following info, where all the trip counts are zero. What am I
doing wrong?
Hello: main
Loop at depth 1 containing: %bb4<header><exiting>,%bb3<latch>,%bb2,%bb,%bb1
Loop at depth 2 containing: %bb2<header><exiting>,%bb1<latch>
BB: bb
Is simplifyed loop? 1
Tripcount 0
Induction variable: printing a <null> value
Loop at depth 2 containing: %bb2<header><exitin...
2013 Oct 10
2
[LLVMdev] Are there implicit rules or conventions for an llvm frontend to generate llvm IR?
...ONLY ONE ReturnInst(and NO InvokeInst) for such
llvm IR; is it legal to add other *ReturnInst*s when transforming?
2. Is it possible for a frontend to generate a function whose CFG is
something like:
bb0
/ \
bb1 bb2
/ \ / \
bb3 bb4 bb5
\ | /
\ | /
\ | /
bb6
(In this case, if I understand correctly, bb4 is control dependent on both
bb1 and bb2.)
I think it at least possible in theory, and there is a simple case:
int foo(int i) {
if (i < 0)...
2016 Sep 21
2
Propagation of debug information for variable into basic blocks.
>
>
> Conceptually, the LiveDebugValues data flow analysis should be using
> three-valued logic arranged in a lattice
>
> ⊥ (uninitialized / don't know)
> / \
> true false (is (not) available)
>
> where join(x, ⊥) = x, otherwise it behaves like boolean &.
>
> All debug variable values are initialized to the bottom element first.
> After
2010 Aug 02
2
[LLVMdev] indirectbr and phi instructions
Hi,
How does the requirement that phi instructions have one value per
predecessor basic block interact with indirectbr instructions? For
instance, take the following code:
L1:
br i1 %somevalue, label %L2, label %L3
L2:
%ret1 = i8* blockaddress(@myfunction, %L5)
br label %L4
L3:
%ret2 = i8* blockaddress(@myfunction, %L6)
br label %L4
L4:
%ret = phi i8* [%ret1, L2], [%ret2, L3]
2009 Aug 28
1
[LLVMdev] va_arg
...next, %bb5 ]
; <i32> [#uses=1]
%sum.012 = phi i32 [ 0, %bb.nph ], [ %14, %bb5 ]
; <i32> [#uses=1]
%4 = load i32* %1, align 8 ; <i32> [#uses=3]
%5 = icmp ult i32 %4, 48 ; <i1> [#uses=1]
br i1 %5, label %bb3, label %bb4
bb3: ; preds = %bb
%6 = load i8** %2, align 8 ; <i8*> [#uses=1]
%7 = inttoptr i32 %4 to i8* ; <i8*> [#uses=1]
%8 = ptrtoint i8* %7 to i64 ; <i64> [#uses=1]
%ctg2 = getelementptr i8* %6, i64 %8...