Displaying 8 results from an estimated 8 matches for "bb2_2".
Did you mean:
bb0_2
2013 Mar 01
4
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...%fl3, %fl1, 0dBFF0000000000000;
> > mov.f64 %fl1, 0d0000000000000000;
> > mov.f64 %fl5, %fl1;
> > mov.f64 %fl4, %fl1;
> > bra.uni BB2_1;
> > BB2_2:
> > add.f64 %fl1, %fl1, 0d3FF0000000000000;
> > sub.f64 %fl6, %fl6, %fl7;
> > add.f64 %fl6, %fl6, %fl2;
> > add.f64 %fl5, %fl5, %fl5;
> >...
2006 Nov 03
0
[LLVMdev] is createCFGSimplificationPass unused?
...t %bar(int %x) {
%b = seteq int %x, 5
br bool %b, label %t, label %f
t:
ret int 1
f:
ret int 2
}
compiles to:
foo:
lda $0,3($31)
zapnot $16,15,$1
cmpeq $1,5,$1
cmoveq $1,7,$0
ret $31,($26),1
bar:
zapnot $16,15,$0
cmpeq $0,5,$0
beq $0,$BB2_2 #f
$BB2_1: #t
lda $0,1($31)
ret $31,($26),1
$BB2_2: #f
lda $0,2($31)
ret $31,($26),1
Which is not a problem with the instruction selector's use of cmov.
It is that the IR is using a branch not a select. SimplifyCFG was
creating selects in the IR, which instru...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...000000;
> > > mov.f64 %fl1, 0d0000000000000000;
> > > mov.f64 %fl5, %fl1;
> > > mov.f64 %fl4, %fl1;
> > > bra.uni BB2_1;
> > > BB2_2:
> > > add.f64 %fl1, %fl1, 0d3FF0000000000000;
> > > sub.f64 %fl6, %fl6, %fl7;
> > > add.f64 %fl6, %fl6, %fl2;
> > > add.f64 %fl5, %fl5...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...00000000000;
>> > mov.f64 %fl1, 0d0000000000000000;
>> > mov.f64 %fl5, %fl1;
>> > mov.f64 %fl4, %fl1;
>> > bra.uni BB2_1;
>> > BB2_2:
>> > add.f64 %fl1, %fl1, 0d3FF0000000000000;
>> > sub.f64 %fl6, %fl6, %fl7;
>> > add.f64 %fl6, %fl6, %fl2;
>> > add.f64 %fl5, %fl5, %f...
2013 Mar 01
1
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...; > mov.f64 %fl1, 0d0000000000000000;
> >> > mov.f64 %fl5, %fl1;
> >> > mov.f64 %fl4, %fl1;
> >> > bra.uni BB2_1;
> >> > BB2_2:
> >> > add.f64 %fl1, %fl1,
> 0d3FF0000000000000;
> >> > sub.f64 %fl6, %fl6, %fl7;
> >> > add.f64 %fl6, %fl6, %fl2;
> >> > add.f64...
2006 Nov 03
4
[LLVMdev] is createCFGSimplificationPass unused?
It looks like createCFGSimplificationPass was disabled on 2006/09/04.
This causes some problems for architectures that use conditional moves
to implement select (alpha and ARM). For example, on 2006/09/03 a "if
(a) return 0; else return 1;" compiled to
----------------------------------------
zapnot $17,15,$1
zapnot $16,15,$2
bis $31,$31,$0
cmpeq $2,$1,$1
2013 Mar 01
2
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...00000;
div.rn.f64 %fl1, %fl4, %fl1;
add.f64 %fl1, %fl1, %fl1;
add.f64 %fl3, %fl1, 0dBFF0000000000000;
mov.f64 %fl1, 0d0000000000000000;
mov.f64 %fl5, %fl1;
mov.f64 %fl4, %fl1;
bra.uni BB2_1;
BB2_2:
add.f64 %fl1, %fl1, 0d3FF0000000000000;
sub.f64 %fl6, %fl6, %fl7;
add.f64 %fl6, %fl6, %fl2;
add.f64 %fl5, %fl5, %fl5;
mul.f64 %fl4, %fl5, %fl4;
add.f64 %fl4, %fl4, %fl3;
mov.f64 %fl5, %f...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl3, %fl1, 0dBFF0000000000000;
>聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl1, 0d0000000000000000;
>聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl1;
>聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl4, %fl1;
>聽 聽 聽 聽 聽 聽 聽 聽 bra.uni聽 聽 聽 聽 聽 聽 聽 聽 BB2_1;
> BB2_2:
>聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl1, %fl1, 0d3FF0000000000000;
>聽 聽 聽 聽 聽 聽 聽 聽 sub.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl7;
>聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl2;
>聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl5, %fl5;
>聽 聽 聽 聽 聽 聽 聽 聽 mul.f64聽 聽...