search for: bb2_1

..., i64 2 %a_val = load i64* %8, align 8 call void @showValue(i64 %a_val) %9 = trunc i64 %a_val to i32 %10 = inttoptr i64 %a_val to [2 x i32]* br label %bb4_1 fun 1_subloop_1 bb_1 bb_1: ; preds = %bb4_1 br i1 undef, label %bb1_1, label %bb2_1 fun 1_subloop_1 bb1_1 bb1_1: ; preds = %bb_1 %t15_1 = load i32* %7, align 4 %t16_1 = getelementptr inbounds [2 x i32]* %10, i32 0, i32 %t15_1 %t17_1 = load i32* %t16_1, align 4 %t19_1 = mul nsw i32 %t17_1, undef %t19_1_64 = sext i32 %t1...

...4 %fl3, %fl1, 0dBFF0000000000000; > > mov.f64 %fl1, 0d0000000000000000; > > mov.f64 %fl5, %fl1; > > mov.f64 %fl4, %fl1; > > bra.uni BB2_1; > > BB2_2: > > add.f64 %fl1, %fl1, 0d3FF0000000000000; > > sub.f64 %fl6, %fl6, %fl7; > > add.f64 %fl6, %fl6, %fl2; > > add.f64 %fl5, %fl5, %...

Hi, All I want to implement DSWP Which is used for parallelization of loops. For this purpose, the loop was replaced with a new basic block in main function. And new functions were created and basic blocks of Loop assigned to them.I have checked blocks and branches for Succ and Pred relation and I have not found any problems. However I get the following error: * **opt:

...l3, %fl1, 0dBFF0000000000000; > > > mov.f64                                %fl1, 0d0000000000000000; > > > mov.f64                                %fl5, %fl1; > > > mov.f64                                %fl4, %fl1; > > > bra.uni                                BB2_1; > > > BB2_2: > > > add.f64                                %fl1, %fl1, 0d3FF0000000000000; > > > sub.f64                                %fl6, %fl6, %fl7; > > > add.f64                                %fl6, %fl6, %fl2; > > > add.f64                     ...

...%fl3, %fl1, 0dBFF0000000000000; >> > mov.f64 %fl1, 0d0000000000000000; >> > mov.f64 %fl5, %fl1; >> > mov.f64 %fl4, %fl1; >> > bra.uni BB2_1; >> > BB2_2: >> > add.f64 %fl1, %fl1, 0d3FF0000000000000; >> > sub.f64 %fl6, %fl6, %fl7; >> > add.f64 %fl6, %fl6, %fl2; >> > add.f64...

...000000000000; > >> > mov.f64 %fl1, 0d0000000000000000; > >> > mov.f64 %fl5, %fl1; > >> > mov.f64 %fl4, %fl1; > >> > bra.uni BB2_1; > >> > BB2_2: > >> > add.f64 %fl1, %fl1, > 0d3FF0000000000000; > >> > sub.f64 %fl6, %fl6, %fl7; > >> > add.f64 %fl6, %fl6, %fl2; > >> >...

...000000000000; div.rn.f64 %fl1, %fl4, %fl1; add.f64 %fl1, %fl1, %fl1; add.f64 %fl3, %fl1, 0dBFF0000000000000; mov.f64 %fl1, 0d0000000000000000; mov.f64 %fl5, %fl1; mov.f64 %fl4, %fl1; bra.uni BB2_1; BB2_2: add.f64 %fl1, %fl1, 0d3FF0000000000000; sub.f64 %fl6, %fl6, %fl7; add.f64 %fl6, %fl6, %fl2; add.f64 %fl5, %fl5, %fl5; mul.f64 %fl4, %fl5, %fl4; add.f64 %fl4, %fl4, %fl3; mov.f64 %...

...聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl3, %fl1, 0dBFF0000000000000; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl1, 0d0000000000000000; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl1; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl4, %fl1; >聽 聽 聽 聽 聽 聽 聽 聽 bra.uni聽 聽 聽 聽 聽 聽 聽 聽 BB2_1; > BB2_2: >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl1, %fl1, 0d3FF0000000000000; >聽 聽 聽 聽 聽 聽 聽 聽 sub.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl7; >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl2; >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl5, %fl5; >聽 聽 聽 聽 聽 聽 聽 聽...

...x) { %b = seteq int %x, 5 br bool %b, label %t, label %f t: ret int 1 f: ret int 2 } compiles to: foo: lda $0,3($31) zapnot $16,15,$1 cmpeq $1,5,$1 cmoveq $1,7,$0 ret $31,($26),1 bar: zapnot $16,15,$0 cmpeq $0,5,$0 beq $0,$BB2_2 #f $BB2_1: #t lda $0,1($31) ret $31,($26),1 $BB2_2: #f lda $0,2($31) ret $31,($26),1 Which is not a problem with the instruction selector's use of cmov. It is that the IR is using a branch not a select. SimplifyCFG was creating selects in the IR, which instruction select...

It looks like createCFGSimplificationPass was disabled on 2006/09/04. This causes some problems for architectures that use conditional moves to implement select (alpha and ARM). For example, on 2006/09/03 a "if (a) return 0; else return 1;" compiled to ---------------------------------------- zapnot $17,15,$1 zapnot $16,15,$2 bis $31,$31,$0 cmpeq $2,$1,$1