Displaying 20 results from an estimated 21 matches for "bb1_1".
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lbb1_1
2011 Oct 13
0
[LLVMdev] BasicBlock succ iterator
...entptr i64* %1, i64 2
%a_val = load i64* %8, align 8
call void @showValue(i64 %a_val)
%9 = trunc i64 %a_val to i32
%10 = inttoptr i64 %a_val to [2 x i32]*
br label %bb4_1
fun 1_subloop_1 bb_1
bb_1: ; preds = %bb4_1
br i1 undef, label %bb1_1, label %bb2_1
fun 1_subloop_1 bb1_1
bb1_1: ; preds = %bb_1
%t15_1 = load i32* %7, align 4
%t16_1 = getelementptr inbounds [2 x i32]* %10, i32 0, i32 %t15_1
%t17_1 = load i32* %t16_1, align 4
%t19_1 = mul nsw i32 %t17_1, undef
%t19_1_64...
2013 Mar 01
4
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...4 %fl3, %fl2, 0dBFF0000000000000;
> > mov.f64 %fl2, 0d0000000000000000;
> > mov.f64 %fl5, %fl2;
> > mov.f64 %fl4, %fl2;
> > bra.uni BB1_1;
> > BB1_2:
> > add.f64 %fl2, %fl2, 0d3FF0000000000000;
> > sub.f64 %fl6, %fl6, %fl7;
> > add.f64 %fl6, %fl6, %fl1;
> > add.f64 %fl5, %fl5, %...
2011 Oct 13
6
[LLVMdev] BasicBlock succ iterator
Hi, All
I want to implement DSWP Which is used for parallelization of loops. For
this purpose, the loop was replaced with a new basic block in main function.
And new functions were created and basic blocks of Loop assigned to them.I
have checked blocks and branches for Succ and Pred relation and I have not
found any problems.
However I get the following error:
*
**opt:
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...l3, %fl2, 0dBFF0000000000000;
> > > mov.f64 %fl2, 0d0000000000000000;
> > > mov.f64 %fl5, %fl2;
> > > mov.f64 %fl4, %fl2;
> > > bra.uni BB1_1;
> > > BB1_2:
> > > add.f64 %fl2, %fl2, 0d3FF0000000000000;
> > > sub.f64 %fl6, %fl6, %fl7;
> > > add.f64 %fl6, %fl6, %fl1;
> > > add.f64 ...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...%fl3, %fl2, 0dBFF0000000000000;
>> > mov.f64 %fl2, 0d0000000000000000;
>> > mov.f64 %fl5, %fl2;
>> > mov.f64 %fl4, %fl2;
>> > bra.uni BB1_1;
>> > BB1_2:
>> > add.f64 %fl2, %fl2, 0d3FF0000000000000;
>> > sub.f64 %fl6, %fl6, %fl7;
>> > add.f64 %fl6, %fl6, %fl1;
>> > add.f64...
2013 Mar 01
1
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...000000000000;
> >> > mov.f64 %fl2, 0d0000000000000000;
> >> > mov.f64 %fl5, %fl2;
> >> > mov.f64 %fl4, %fl2;
> >> > bra.uni BB1_1;
> >> > BB1_2:
> >> > add.f64 %fl2, %fl2,
> 0d3FF0000000000000;
> >> > sub.f64 %fl6, %fl6, %fl7;
> >> > add.f64 %fl6, %fl6, %fl1;
> >> >...
2017 Jul 17
2
A bug related with undef value when bootstrap MemorySSA.cpp
...Begin function hoo
74 .p2align 4, 0x90
75 .type hoo, at function
76 hoo: # @hoo
77 .cfi_startproc
78 # BB#0:
79 movq a(%rip), %rax
80 movq cnt(%rip), %rcx
81 cmpq $0, i_hasval(%rip)
82 sete %sil
83 xorl %edx, %edx
84 .p2align 4, 0x90
85 .LBB1_1: # =>This Inner Loop Header:
Depth=1
86 testb $1, %sil
87 je .LBB1_3
88 # BB#2: # in Loop: Header=BB1_1 Depth=1
89 movq b(%rip), %rsi
90 addq %rax, %rsi
91 movq %rsi, c(%rip)
92 movq $3, i_hasval(%rip)
93 incq %...
2013 Mar 01
2
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...tion_param_4;
div.rn.f64 %fl2, %fl2, %fl3;
add.f64 %fl2, %fl2, %fl2;
add.f64 %fl3, %fl2, 0dBFF0000000000000;
mov.f64 %fl2, 0d0000000000000000;
mov.f64 %fl5, %fl2;
mov.f64 %fl4, %fl2;
bra.uni BB1_1;
BB1_2:
add.f64 %fl2, %fl2, 0d3FF0000000000000;
sub.f64 %fl6, %fl6, %fl7;
add.f64 %fl6, %fl6, %fl1;
add.f64 %fl5, %fl5, %fl5;
mul.f64 %fl4, %fl5, %fl4;
add.f64 %fl4, %fl4, %fl3;
mov.f64 %...
2017 Jul 17
3
A bug related with undef value when bootstrap MemorySSA.cpp
...# @hoo
>> 77 .cfi_startproc
>> 78 # BB#0:
>> 79 movq a(%rip), %rax
>> 80 movq cnt(%rip), %rcx
>> 81 cmpq $0, i_hasval(%rip)
>> 82 sete %sil
>> 83 xorl %edx, %edx
>> 84 .p2align 4, 0x90
>> 85 .LBB1_1: # =>This Inner Loop Header:
>> Depth=1
>> 86 testb $1, %sil
>> 87 je .LBB1_3
>> 88 # BB#2: # in Loop: Header=BB1_1
>> Depth=1
>> 89 movq b(%rip), %rsi
>> 90 addq %rax, %rsi
>...
2017 Jul 17
3
A bug related with undef value when bootstrap MemorySSA.cpp
...;> >> 78 # BB#0:
>> >> 79 movq a(%rip), %rax
>> >> 80 movq cnt(%rip), %rcx
>> >> 81 cmpq $0, i_hasval(%rip)
>> >> 82 sete %sil
>> >> 83 xorl %edx, %edx
>> >> 84 .p2align 4, 0x90
>> >> 85 .LBB1_1: # =>This Inner Loop Header:
>> >> Depth=1
>> >> 86 testb $1, %sil
>> >> 87 je .LBB1_3
>> >> 88 # BB#2: # in Loop: Header=BB1_1
>> >> Depth=1
>> >> 89 m...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl3, %fl2, 0dBFF0000000000000;
>聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl2, 0d0000000000000000;
>聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl2;
>聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl4, %fl2;
>聽 聽 聽 聽 聽 聽 聽 聽 bra.uni聽 聽 聽 聽 聽 聽 聽 聽 BB1_1;
> BB1_2:
>聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl2, %fl2, 0d3FF0000000000000;
>聽 聽 聽 聽 聽 聽 聽 聽 sub.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl7;
>聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl1;
>聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl5, %fl5;
>聽 聽 聽 聽 聽 聽 聽 聽...
2006 Oct 18
0
[LLVMdev] emitting jump tables
I am currently able to emit jump tables, but I cannot use then because
I cant figure out how to add its address to the constant pool.
For example, if I have the jump table
-------------------------------------
.JTI1_0:
.word .BB1_6
.word .BB1_7
.word .BB1_1
.word .BB1_2
-------------------------------------
the address ".JTI1_0" must be in a constant pool:
---------------------------------
.xyz
.word .JTI1_0
....
ldr r1, .xyz
add r0, r0, r1
ldr r0, [r0]
bx r0
---------------------------------
I intended to do something simi...
2007 Sep 04
0
[LLVMdev] How to put a pass for last?
..., 56, %g1
save %g1, %o6, %o6
sethi 0, %l0
The nop right before sethi is one instruction I'm not being able to reach in
my pass.
But there is more:
add %l0, 1, %l0
st %l0, [%i6+-12]
.BB1_2: ! bb8
ld [%i6+-12], %l0
subcc %l0, 1000, %l0
bl .BB1_1 ! bb
nop
.BB1_3: ! bb12
ba .BB1_5 ! bb19
nop
or %g0, 1, %l0
Here both the "ba" and the "nop", that are the 3rd and 2nd last operations
of this snipet, are not reachable.
Could I express myself good enougth?
Is it possible to do what...
2017 Jul 18
4
A bug related with undef value when bootstrap MemorySSA.cpp
...movq a(%rip), %rax
>>>> >> 80 movq cnt(%rip), %rcx
>>>> >> 81 cmpq $0, i_hasval(%rip)
>>>> >> 82 sete %sil
>>>> >> 83 xorl %edx, %edx
>>>> >> 84 .p2align 4, 0x90
>>>> >> 85 .LBB1_1: # =>This Inner Loop Header:
>>>> >> Depth=1
>>>> >> 86 testb $1, %sil
>>>> >> 87 je .LBB1_3
>>>> >> 88 # BB#2: # in Loop: Header=BB1_1
>>>> &...
2009 Jun 17
2
[LLVMdev] possible PowerPC (32bits) backend bug
...= a - b;
return 0;
}
And here is the assembly:
<Insert the pPPC assembly here>
.text
.global main
.type main, @function
.align 2
main:
lfs 0, -8(1)
lfs 1, -12(1)
li 3, 0
fmuls 2, 1, 0
stfs 2, -12(1)
lfs 2, -16(1)
fnmsubs 0, 1, 0, 2
stfs 0, -16(1)
stw 3, -20(1)
stw 3, -4(1)
BB1_1: # return
lwz 3, -4(1)
blr
.size main,.-main
At a glance, it looks right. Line 12 is, indeed the "fnmsubs" command, so
the pattern did work. But look at Line 9. Here we see that the "fmuls"
also happened! In effect, this means that the fmul happens TWICE.
That can&...
2017 Jul 18
2
A bug related with undef value when bootstrap MemorySSA.cpp
...; 80 movq cnt(%rip), %rcx
> >>>> >> 81 cmpq $0, i_hasval(%rip)
> >>>> >> 82 sete %sil
> >>>> >> 83 xorl %edx, %edx
> >>>> >> 84 .p2align 4, 0x90
> >>>> >> 85 .LBB1_1: # =>This Inner Loop Header:
> >>>> >> Depth=1
> >>>> >> 86 testb $1, %sil
> >>>> >> 87 je .LBB1_3
> >>>> >> 88 # BB#2: # in Loop: Header=BB1_1
> >>>...
2006 Nov 03
4
[LLVMdev] is createCFGSimplificationPass unused?
...,$2
bis $31,$31,$0
cmpeq $2,$1,$1
cmoveq $1,1,$0
ret $31,($26),1
----------------------------------------
Now it compiles to
----------------------------------
zapnot $17,15,$0
zapnot $16,15,$1
cmpeq $1,$0,$0
beq $0,$BB1_2 #return
$BB1_1: #cond_true
bis $31,$31,$0
ret $31,($26),1
$BB1_2: #return
lda $0,1($31)
ret $31,($26),1
----------------------------------
I have added createCFGSimplificationPass in
ARMTargetMachine::addInstSelector to fix this problem. Is this the
correct solution? I think that...
2017 Jul 16
2
A bug related with undef value when bootstrap MemorySSA.cpp
...inside of it, and it is wrong.
hoo: # @hoo
.cfi_startproc
# BB#0: # %entry
movq cnt(%rip), %rax
cmpq $0, i_hasval(%rip)
sete %dl
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %do.body.us.i
# =>This Inner Loop Header: Depth=1
testb $1, %dl
je .LBB1_3
# BB#2: # %if.end2.us.i
# in Loop: Header=BB1_1 De...
2017 Jul 17
3
A bug related with undef value when bootstrap MemorySSA.cpp
On Mon, Jul 17, 2017 at 11:18 AM, Sanjoy Das via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi,
>
> On Mon, Jul 17, 2017 at 10:32 AM, Xinliang David Li <davidxl at google.com>
> wrote:
> > The issue blocks another optimization patch and Wei has spent huge
> amount of
> > effort isolating the the bootstrap failure to this same problem. I agree
> >
2010 Jan 28
2
[LLVMdev] llc generated machine assembly code for NASM
...e".
.686
.MMX
.XMM
.model flat
EXTERN _abort:near
.text
public _foo
ALIGN 16
_foo proc near
sub ESP, 8
$label1:
mov EAX, DWORD PTR [ESP + 12]
mov DWORD PTR [ESP], EAX
mov DWORD PTR [ESP + 4], 0
mov EAX, DWORD PTR [ESP]
mov DWORD PTR [_gv], EAX
cmp DWORD PTR [ESP], 6
jb $BB1_4
$BB1_1: ; %then
mov DWORD PTR [ESP + 4], 0
ALIGN 16
$BB1_2: ; %while
; Loop Depth 1...