Displaying 2 results from an estimated 2 matches for "bb0_4".
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lbb0_4
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...r6, r19, 44
beqid r7, ($BB0_2)
swi r8, r19, 48
lwi r3, r19, 40
swi r3, r19, 48
$BB0_2:
lwi r3, r19, 48
lwi r4, r19, 44
lwi r5, r19, 36
swi r3, r19, 52
beqid r5, ($BB0_4)
swi r4, r19, 56
lwi r3, r19, 40
swi r3, r19, 56
$BB0_4:
lwi r3, r19, 56
lwi r4, r19, 44
lwi r5, r19, 32
swi r3, r19, 60
bgtid r5, ($BB0_6)
swi r4, r19, 64
l...
2014 May 10
6
[LLVMdev] Replacing Platform Specific IR Codes with Generic Implementation and Introducing Macro Facilities
On 10 May 2014, at 13:53, Tim Northover <t.p.northover at gmail.com> wrote:
> It doesn't make sense for everything though, particularly if you want
> target-specific IR to simply not exist. What would you map ARM's
> "ldrex" to on x86?
This isn't a great example. Having load-linked / store-conditional in the IR would make a number of transforms related to