Displaying 6 results from an estimated 6 matches for "basicblocksdnod".
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basicblocksdnode
2010 Jun 09
3
[LLVMdev] [llvmdev] Whole function SelectionDAG
At first I'll try the simplest strategy: put the instruction in the machine
BB corresponding to the LLVM BB where it comes from.
To implement this, I plan to add an operand to non-passive node which points
to the BasicBlockSDNode which the node belongs to.
Another idea is to use a side map to map each node to its block. But I guess
it's difficult to keep the map consistent when transforming the DAG.
On Wed, Jun 9, 2010 at 1:39 AM, Dan Gohman <gohman at apple.com> wrote:
> The first question is code placemen...
2010 Jun 11
0
[LLVMdev] [llvmdev] Whole function SelectionDAG
I have another idea: let the BasicBlockSDNode points to the last node in its
predecessor blocks. But this will introduce cycles into the selection DAG,
making it not a DAG anymore.
So what's the impact of a non-DAG on the existing DAG legalizers and
combiner?
On Wed, Jun 9, 2010 at 9:33 AM, Zhongxing Xu <xuzhongxing at gmail.com>...
2010 Jun 11
1
[LLVMdev] [llvmdev] Whole function SelectionDAG
On Jun 11, 2010, at 12:48 AM, Zhongxing Xu <xuzhongxing at gmail.com>
wrote:
> I have another idea: let the BasicBlockSDNode points to the last
> node in its predecessor blocks. But this will introduce cycles into
> the selection DAG, making it not a DAG anymore.
>
> So what's the impact of a non-DAG on the existing DAG legalizers and
> combiner?
Lots of stuff would break, for example anything...
2010 Jun 08
0
[LLVMdev] [llvmdev] Whole function SelectionDAG
The first question is code placement. How is the compiler going to
decide which block (or blocks) to emit an instruction in? The answer
to that will help determine how control relationships should be
represented.
Dan
On Jun 7, 2010, at 11:56 PM, Zhongxing Xu <xuzhongxing at gmail.com> wrote:
> I am trying to build a DAG for a whole function. The first problem I
> met is to
2012 Dec 17
0
[LLVMdev] Query Regarding instruction ordering of passive nodes
...uled during instruction scheduling such that they are free to be placed anywhere while generating the instruction sequence. Is this related with above problem of debug location ?
The list of passive nodes are :-
ConstantSDNode
ConstantFPSDNode
RegisterSDNode
RegisterMaskSDNode
GlobalAddressSDNode
BasicBlockSDNode
FrameIndexSDNode
ConstantPoolSDNode
JumpTableSDNode
ExternalSymbolSDNode
BlockAddressSDNode
MDNodeSDNode
Thanks
Karthik
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2010 Jun 08
2
[LLVMdev] [llvmdev] Whole function SelectionDAG
I am trying to build a DAG for a whole function. The first problem I met is
to assign a user for the last instruction of each basic block, be it BRCOND
or other node. There is no natural user for such nodes. Without user, it
will be removed in later phases. My idea is to use it as chain for nodes in
the next basic block. Is this reasonable?
-Zhongxing Xu
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