search for: base_reg

Hi all, On behalf of Andes Technology Corp, I am proposing a backend targeting the NDS32 V3 ISA. NDS32 V3 ISA is a 16/32 bit mixed instruction set architecture that developed By AndesTech. You can find more information at the Andes website <http://www.andestech.com/>, and reference AndeStar ISA Manual (V3 ISA) from document download page <http://www.andestech.com/product.php?cls=9>.

...ster and status bits written. The result can also be %null meaning that the result is only written to the accumulator. Defining all the possible operand formats in separate instruction definitions would result in a huge number of instructions. The addressing modes are defined like this: offset[%base_reg, %index_reg] One, two or all three can be defined and the offset can be a relocatable symbol or a signed int. Memory operands need not be introduced until just before register allocation (maybe they couldn't be?). Any suggestions on how to attack this problem would be greatly appreciated. -...

Hi, I've been trying to teach LLVM that pointers are 128-bit long, which segfaults with some seemingly unrelated stacktrace when I try to take an address of a variable. Since stack saving and loading seems to work fine, I dare to assume the instruction causing problems there is leaq. Now I've done a search for leaq of the entire LLVM codebase with no success and I'd like to know which