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...egisterClass(MVT::i128, &X86::PR128RegClass); and in findRepresentativeClass(): case MVT::i128: RRC = &X86::PR128RegClass; But even though my nodes have MVT::i128 value type, they get allocated to XMM registers. I have, of course, removed i128 from FR128. What am I missing? Thanks, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180122/b39a7108/attachment.html>

...28, (sequence "POI%u", 0, 7)>; However, my debug message in TargetLowering base in its method computeRegisterProperties shows that RegClassForVT[MVT::i128] is still a nullptr. What else should I add for my registers to be a proper destination location of all 128-bit integers? Thanks, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180119/4d7bff1a/attachment.html>

...cess and I'd like to know which DAG nodes and eventually instructions does the last store in the following piece of code get translated to before it gets emitted. %1 = alloca i32, align 4 %2 = alloca i32*, align 8 store i32 10, i32* %1, align 4 store i32* %1, i32** %2, align 8 Thanks, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180118/0430505d/attachment.html>

...t;Before you invest a significant amount of effort into a non-trivial extension, *ask on the list*" so that's what I'm doing. I would like to know which of the solutions would work in my case and what's the easiest way to achieve my goal. Thank you very much! -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20171211/45d5ecc9/attachment.html>

...e invocation) Now I know almost nothing about LLVM, but I assumed that since X86 target has SSE extensions, it wouldn't have a problem with a 128-bit value type in general. I would really appreciate any explanations and pointers you can give me. Sorry for such a general question. Best wishes, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180116/7f7fef34/attachment.html>

Hi, I would like to wrap some of the library functions such as malloc() into for example: malloc_wrapper(int size) { malloc(size+4); //call the real malloc here } and have all uses of malloc replaced with malloc_wrapper. Is there a way to do that? -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 <+421%20905%20718%20390> UK: +447477833795 <+44%207477%20833795> -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20171227/8d1d3fdd/attachment.h...

Hi all, the backend data layout string is generated in X86TargetMachine.cpp. As far as I understand, however, that is not the only place where the target description string is generted. Where does the expected target description string come from? Thanks! -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180110/1e58bff8/attachment.html>

...h of the entire codebase and found that all creation of CopyToReg nodes happens at SelectionDAG.h, eventually, but my debug messages did not register a call to either of the three getCopyToReg methods it provides. Is there any other place where CopyToReg nodes get generated for x86 target? Thanks, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180216/665ef340/attachment.html>

...4(%rbp), %rcx movq %rcx, %poi2 movaps %poi2, (%poi1) bndmov %poi0, -48(%rbp) # 16-byte Folded Spill popq %rbp retq The instructions in red should not be there, otherwise, everything is fine. Does anyone know what could be causing this? Thanks, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180129/fcefb7ff/attachment.html>