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> On 2015-Jun-04, at 12:45, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > >> On 2015-Jun-04, at 12:28, Ivan Baev <ibaev at codeaurora.org> wrote: >> >> Hi, we got the following assert: >> >> assert(!Working[0].isLoopHeader() && "entry block is a loop header"); >> >> [in BlockFrequencyInfoImpl<BT>::tryToComputeMassInFunction(), >> Block...

> Date: Tue, 14 Apr 2015 21:33:03 -0700 > From: "Duncan P. N. Exon Smith" <dexonsmith at apple.com> > To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Subject: [LLVMdev] RFC: Metadata attachments to function definitions > Message-ID: <BF4002F0-06DC-4A25-AF84-7D21AD48121A at apple.com> > Content-Type: text/plain; charset=us-ascii > >

On 04/15/15 12:55, Duncan P. N. Exon Smith wrote: >> On 2015-Apr-15, at 08:11, Ivan Baev <ibaev at codeaurora.org> wrote: >> >>> Date: Tue, 14 Apr 2015 21:33:03 -0700 >>> From: "Duncan P. N. Exon Smith" <dexonsmith at apple.com> >>> To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >>> Subject: [LLVMdev] RFC:...

Hi, we got the following assert: assert(!Working[0].isLoopHeader() && "entry block is a loop header"); [in BlockFrequencyInfoImpl<BT>::tryToComputeMassInFunction(), BlockFrequencyInfoImpl.h] on a Hexagon target - the entry block is a loop header. Has someone seen this assert on other targets? What would be a preferable way to fix it: - extend BlockFrequency pass to

...on III & IV Welcome, Tanya Lattner - LLVM Foundation WebAssembly: Here Be Dragons, Jf Bastien - Google, Dan Gohman - Mozilla A Proposal for Global Instruction Selection, Quentin Colombet - Apple Session #2: October 29 11:00-12:30 Salon III & IV Profile-based Indirect Call Promotion, Ivan Baev - QuIC Automated performance-tracking of LLVM-generated code, Kristof Beyls - ARM Session #3: October 29 11:00-12:30: Salon I & II Beyond Sanitizers: guided fuzzing and security hardening, Kostya Serebryany - Google A Heterogeneous Execution Engine for LLVM, Christos Margiolas - University of...

...rofile infrastructure http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084271.html Your feedback and comments will be highly appreciated. Thanks, Ivan ============================================================================RFC: Indirect Call Promotion LLVM Pass Betul Buyukkurt and Ivan Baev 1. Introduction Indirect call promotion (ICP) replaces an indirect call instruction to a set of target addresses with a sequence of tests guarding direct calls to selected targets, plus a fall through branch containing the original indirect call. The ICP optimization is found to be the second most...

...4imm. > The bottom line is, our rematerialization scheme is currently > limited, but I am not sure your proposal get us beyond what we > already support. I might have misunderstood the proposal, but why do you say that? The problem is not limited to constants (as perhaps evidenced by Ivan Baev's talk at the 2014 dev meeting). One basic thing we should get, for example, is: q = ...; r = ...; for (...) { // complicated stuff foo(q, r, q - r); // should prefer to remat (q-r) here instead of spilling. } Also, this is all perhaps related to https://llvm.org/bugs/show_bug.cgi?id=2...

...e patches for review will be posted soon. RFC: [DebugInfo] Improving Debug Information in LLVM to Recover Optimized-out Function Parameters Ananthakrishna Sowda(Cisco), asowda at cisco.com Nikola Prica (RT-RK/Cisco), nprica at rtrk.com Djordje Todorovic(RT-RK/Cisco), djtodorovic at rtrk.com Ivan Baev (Cisco), ibaev at cisco.com Overview of the problem Software release products are compiled with optimization level –O2 and higher. Such products might produce a core-file in case of a failure. Support engineers usually begin debug analysis by looking at the backtrace from a core-file. Unfortunat...

...C: [DebugInfo] Improving Debug Information in LLVM to Recover Optimized-out Function Parameters > > Ananthakrishna Sowda(Cisco), asowda at cisco.com > Nikola Prica (RT-RK/Cisco), nprica at rtrk.com > Djordje Todorovic(RT-RK/Cisco), djtodorovic at rtrk.com > Ivan Baev (Cisco), ibaev at cisco.com > > > Overview of the problem > Software release products are compiled with optimization level –O2 and higher. Such products might produce a core-file in case of a failure. Support engineers usually begin debug analysis by looking at the ba...

On Mon, Sep 19, 2016 at 6:21 PM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > I've been looking at this myself for ARM, and came up with a much simpler > solution: lower immediate materializations to a post-RA pseudo and expand > the chain of materialization instructions after register allocation / > remat. Remat only sees one instruction with no

...o Recover > Optimized-out Function Parameters > > > > Ananthakrishna Sowda(Cisco), asowda at cisco.com > > Nikola Prica (RT-RK/Cisco), nprica at rtrk.com > > Djordje Todorovic(RT-RK/Cisco), djtodorovic at rtrk.com > > Ivan Baev (Cisco), ibaev at cisco.com > > > > > > Overview of the problem > > Software release products are compiled with optimization level –O2 > and higher. Such products might produce a core-file in case of a failure. > Support engineer...

Hello LLVM Developers, We are working on extending currently available register rematerialization to include cases where sequence of multiple instructions is required to rematerialize a value. We had a discussion on this in community mailing list and link is here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/subject.html#104777 >From the above discussion and studying the code we