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...ese changes! Thanks for working on it. On Fri, Oct 11, 2013 at 10:32 PM, Bill Wendling <isanbard at gmail.com> wrote: > Hi Dmitry, > > I can try my best, but it would be a bit tricky to get it all finished by > then... > > -bw > > On Oct 11, 2013, at 4:10 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > Bill, > > Are there any chances that you complete it before 3.4 is branched? > > > On Thu, Oct 10, 2013 at 10:16 PM, Bill Wendling <isanbard at gmail.com>wrote: > >> On Oct 10, 2013, at 4:22 AM, Dmitry Babokin <babokin a...

FYI: http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-October/066389.html Please read and let me know you comments. -bw On Oct 11, 2013, at 2:47 PM, Dmitry Babokin <babokin at gmail.com> wrote: > Looking forward to these changes! Thanks for working on it. > > > On Fri, Oct 11, 2013 at 10:32 PM, Bill Wendling <isanbard at gmail.com> wrote: > Hi Dmitry, > > I can try my best, but it would be a bit tricky to get it all finish...

Bill, Are there any chances that you complete it before 3.4 is branched? On Thu, Oct 10, 2013 at 10:16 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Oct 10, 2013, at 4:22 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > > Bill, > > > > Thanks for answering. To make sure that we are on the same page, let's > agree on definitions :) Here, by fat binaries I mean the binary, where some > functions are compiled for one flavor of x86, while others ar...

Hi Dmitry, I can try my best, but it would be a bit tricky to get it all finished by then... -bw On Oct 11, 2013, at 4:10 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Bill, > > Are there any chances that you complete it before 3.4 is branched? > > > On Thu, Oct 10, 2013 at 10:16 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Oct 10, 2013, at 4:22 AM, Dmitry Babokin <babokin at gmail.c...

...s around this problem by > expanding the mask to i32s and using intrinsics. Can you please verify that > this regression only happens on AVX ? Can you change ISPC to use intrinsics > ? > > Thanks > Nadav > > Sent from my iPhone > > > On Oct 21, 2013, at 4:04, Dmitry Babokin <babokin at gmail.com> wrote: > > > > Nadav, > > > > Could you please have a look at bug #16941 and let us know what you > think about it? It's performance regression after one of your commits. > > > > Thanks. > > > > Dmitry. > -------...

...e mask and operand type. Why does > ISPC generate illegal vector types ? Does ISPC rely on the LLVM codegen to > split the vectors to increase ILP ? In that case ISPC should generate two > vectors operations. > > Thanks, > Nadav > > > On Oct 25, 2013, at 2:16 PM, Dmitry Babokin <babokin at gmail.com> wrote: > > Nadav, > > The problem appears only for vectors longer than available hardware > register (in doubleword elements, i.e. more than 4 on SSE4 and more than 8 > on AVX). Select does weird thing. <8 x i1> mask comes as two XMM registers, &...

...ed because LLVM did not support vector-selects when this code was written. Can you submit a small SSE4 test case that demonstrates the problem? Select is the canonical form of this operations, and SEXT is usually more difficult to lower. Thanks, Nadav On Oct 21, 2013, at 11:12 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Nadav, > > You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. > > We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM i...

...files with vectors of length 4, 8 and 16. Try 4 on SEE4 and you'll see that both cases work well, 8 demonstrates the difference on SSE4. The same on AVX (8 vs 16). On Wed, Oct 23, 2013 at 1:41 AM, Nadav Rotem <nrotem at apple.com> wrote: > > On Oct 21, 2013, at 12:09 PM, Dmitry Babokin <babokin at gmail.com> wrote: > > By the way, I'm curious, is the any reason why you focus on SSE4, not AVX? > Seems that vectorizer should care the most about the latest silicon. > > > I am interested in looking at the SSE4 code because lowering of AVX code > is more...

...way to support instructions that mix the mask and operand type. Why does ISPC generate illegal vector types ? Does ISPC rely on the LLVM codegen to split the vectors to increase ILP ? In that case ISPC should generate two vectors operations. Thanks, Nadav On Oct 25, 2013, at 2:16 PM, Dmitry Babokin <babokin at gmail.com> wrote: > Nadav, > > The problem appears only for vectors longer than available hardware register (in doubleword elements, i.e. more than 4 on SSE4 and more than 8 on AVX). Select does weird thing. <8 x i1> mask comes as two XMM registers, select convert...

...elects when this code was > written. > > Can you submit a small SSE4 test case that demonstrates the problem? > Select is the canonical form of this operations, and SEXT is usually more > difficult to lower. > > Thanks, > Nadav > > On Oct 21, 2013, at 11:12 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > Nadav, > > You are absolutely right, it's ISPC workload. I've checked SSE4 and it's > also severely affected. > > We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. > For the rest we use ge...

On 06/28/2017 02:41 PM, Dmitry Babokin via llvm-dev wrote: > I've also switched to https and it solved the problem. > > With http, it's still failing almost always, when I'm behind corporate > proxy. And it does work when I'm not behind the proxy. Not sure if > it's a problem of the proxy, or it'...

...test scripts still expect a UNIX-like environment, so a lot of tests fail. > If that has been rectified, someone please let me know! > > I would imagine it should work much better with cygwin, or mingw with a bash > shell and utils. > > > On Fri, Feb 8, 2013 at 11:29 AM, Dmitry Babokin <babokin at gmail.com> wrote: >> >> Hello, >> >> I'm compiling llvm+clang (both are 3.2) on Windows using CMake + VS2010 >> (SP1). I have ALL_BUILD successfully passing, but "check-all" fails. Is it >> expected to pass? Is it expected to pass...

...hat were noticed by Ben. Please correct me if my understanding is wrong. So do I understand you correctly, that your new solution supposed to solve this problem? Dmitry. On Thu, Oct 10, 2013 at 12:34 AM, Bill Wendling <isanbard at gmail.com> wrote: > On Oct 3, 2013, at 9:34 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > Bill, Ben, everyone, > > Some time ago "target-features" and "target-cpu" attributes were > introduced. As I understand, they are intended to support generation of > "fat binaries" (binaries with functions gener...

...help' to     llvmdev-request at cs.uiuc.edu You can reach the person managing the list at     llvmdev-owner at cs.uiuc.edu When replying, please edit your Subject line so it is more specific than "Re: Contents of LLVMdev digest..." Today's Topics:   1. Re: Bug #16941 (Dmitry Babokin)   2. Re: Bug #16941 (Nadav Rotem)   3. Re: Feature request for include llvm-mc in llvm.org/builds       (Reid Kleckner)   4. Re: Feature request for include llvm-mc in llvm.org/builds       (Reid Kleckner)   5. Re: Bug #16941 (Dmitry Babokin)   6. Re: First attempt at recognizing pointer redu...

...dows with MSVC was a PITA. The test scripts still expect a UNIX-like environment, so a lot of tests fail. If that has been rectified, someone please let me know! I would imagine it should work much better with cygwin, or mingw with a bash shell and utils. On Fri, Feb 8, 2013 at 11:29 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Hello, > > I'm compiling llvm+clang (both are 3.2) on Windows using CMake + VS2010 > (SP1). I have ALL_BUILD successfully passing, but "check-all" fails. Is it > expected to pass? Is it expected to pass on Windows with any other &g...

Nadav, Could you please have a look at bug #16941 and let us know what you think about it? It's performance regression after one of your commits. Thanks. Dmitry. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131021/036e81d6/attachment.html>

...and 256 bit registers are available. ISPC works around this problem by expanding the mask to i32s and using intrinsics. Can you please verify that this regression only happens on AVX ? Can you change ISPC to use intrinsics ? Thanks Nadav Sent from my iPhone > On Oct 21, 2013, at 4:04, Dmitry Babokin <babokin at gmail.com> wrote: > > Nadav, > > Could you please have a look at bug #16941 and let us know what you think about it? It's performance regression after one of your commits. > > Thanks. > > Dmitry.

...attner via llvm-dev <llvm-dev at lists.llvm.org> wrote: > I haven’t gotten a lot of people mentioning this specific error, so I hope > others will speak up. > > What version of the svn client are you using? > > Thanks, > Tanya > > On Jun 27, 2017, at 2:38 PM, Dmitry Babokin <babokin at gmail.com> wrote: > > Hi, > > After the move I have problems with svn checkout of trunk and 4.0 branch. I > get the whole bunch of different errors during checkout, including: > svn: E000054: Error running context: Connection reset by peer > svn: E000060: Oper...

Hello, I'm compiling llvm+clang (both are 3.2) on Windows using CMake + VS2010 (SP1). I have ALL_BUILD successfully passing, but "check-all" fails. Is it expected to pass? Is it expected to pass on Windows with any other toolchain? -Dmitry -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Oct 21, 2013, at 12:09 PM, Dmitry Babokin <babokin at gmail.com> wrote: > By the way, I'm curious, is the any reason why you focus on SSE4, not AVX? Seems that vectorizer should care the most about the latest silicon. > I am interested in looking at the SSE4 code because lowering of AVX code is more complicated, especial...