Displaying 1 result from an estimated 1 matches for "ba38a9af".
2009 Feb 19
1
[LLVMdev] help: about how to use tblgen to constraint operand.
I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: