search for: b_zext

...void @llvm.dbg.declare(metadata i32* %x, metadata !50, metadata !DIExpression()), !dbg !57 ret void, !dbg !58 } You can see this takes advantage of @llvm.sadd.with.overflow, which is not available with vectors. So here is a different approach (pseudocode): %a_zext = zext %a to i33 # 1 more bit %b_zext = zext %b to i33 # 1 more bit %result_zext = add %a_zext, %b_zext %max_result = @llvm.experimental.vector.reduce.umax(%result_zext) %overflow = icmp %max_result > @max_i32_value %result = trunc %result_zext to i32 You can imagine how this would work for signed integers, replacing zext with sext...

Hello, I wanted to ask one general question ( for now it is hard to check it manually, maybe there is a fast answer): can I construct an operation, say, addition, from operand_0 - 5 bits size and operand_1 - 3 bit size -> receive result as 6 bit size . I am basically reducing these sizes in the whole IR, so I want that all operands can have arbitrary sizes ( llvm pass is not really good because

...ression()), !dbg !57 >> ret void, !dbg !58 >> } >> >> You can see this takes advantage of @llvm.sadd.with.overflow, which is >> not available with vectors. So here is a different approach (pseudocode): >> >> %a_zext = zext %a to i33 # 1 more bit >> %b_zext = zext %b to i33 # 1 more bit >> %result_zext = add %a_zext, %b_zext >> %max_result = @llvm.experimental.vector.reduce.umax(%result_zext) >> %overflow = icmp %max_result > @max_i32_value >> %result = trunc %result_zext to i32 >> >> You can imagine how this wou...

...; ret void, !dbg !58 >>> } >>> >>> You can see this takes advantage of @llvm.sadd.with.overflow, which is >>> not available with vectors. So here is a different approach (pseudocode): >>> >>> %a_zext = zext %a to i33 # 1 more bit >>> %b_zext = zext %b to i33 # 1 more bit >>> %result_zext = add %a_zext, %b_zext >>> %max_result = @llvm.experimental.vector.reduce.umax(%result_zext) >>> %overflow = icmp %max_result > @max_i32_value >>> %result = trunc %result_zext to i32 >>> >>> You...