Displaying 16 results from an estimated 16 matches for "b_addr".
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2012 Sep 21
3
[LLVMdev] Alias Analysis accuracy
...rs, 0 call sites
> NoAlias: i32* %a, i32* %b
> NoAlias: i32* %a, i32* %c
> NoAlias: i32* %b, i32* %c
> NoAlias: i32* %a, i32** %a_addr
> NoAlias: i32* %b, i32** %a_addr
> NoAlias: i32* %c, i32** %a_addr
> NoAlias: i32* %a, i32** %b_addr
> NoAlias: i32* %b, i32** %b_addr
> NoAlias: i32* %c, i32** %b_addr
> NoAlias: i32** %a_addr, i32** %b_addr
> NoAlias: i32* %a, i32** %c_addr
> NoAlias: i32* %b, i32** %c_addr
> NoAlias: i32* %c, i32** %c_addr
> NoAlias: i32** %a...
2012 Sep 21
0
[LLVMdev] Alias Analysis accuracy
...AA result:
Function: foo: 13 pointers, 0 call sites
NoAlias: i32* %a, i32* %b
NoAlias: i32* %a, i32* %c
NoAlias: i32* %b, i32* %c
NoAlias: i32* %a, i32** %a_addr
NoAlias: i32* %b, i32** %a_addr
NoAlias: i32* %c, i32** %a_addr
NoAlias: i32* %a, i32** %b_addr
NoAlias: i32* %b, i32** %b_addr
NoAlias: i32* %c, i32** %b_addr
NoAlias: i32** %a_addr, i32** %b_addr
NoAlias: i32* %a, i32** %c_addr
NoAlias: i32* %b, i32** %c_addr
NoAlias: i32* %c, i32** %c_addr
NoAlias: i32** %a_addr, i32** %c_addr
NoAlias:...
2012 Sep 21
0
[LLVMdev] Alias Analysis accuracy
...s: i32* %a, i32* %b
> > NoAlias: i32* %a, i32* %c
> > NoAlias: i32* %b, i32* %c
> > NoAlias: i32* %a, i32** %a_addr
> > NoAlias: i32* %b, i32** %a_addr
> > NoAlias: i32* %c, i32** %a_addr
> > NoAlias: i32* %a, i32** %b_addr
> > NoAlias: i32* %b, i32** %b_addr
> > NoAlias: i32* %c, i32** %b_addr
> > NoAlias: i32** %a_addr, i32** %b_addr
> > NoAlias: i32* %a, i32** %c_addr
> > NoAlias: i32* %b, i32** %c_addr
> > NoAlias: i32* %c, i32** %c_addr...
2012 Sep 21
3
[LLVMdev] Alias Analysis accuracy
Can you give an example? And is this limited to C (not C++) only?
On Fri, Sep 21, 2012 at 2:52 PM, Liu, Yaxun (Sam) <Yaxun.Liu at amd.com> wrote:
> I think you may add restrict type qualifier.****
>
> ** **
>
> Sam****
>
> ** **
>
> *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On
> Behalf Of *Welson Sun
> *Sent:* Friday,
2012 Sep 21
3
[LLVMdev] Alias Analysis accuracy
...8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu"
define void @_Z3fooPiS_S_(i32* %a, i32* %b, i32* %c) nounwind {
entry:
%a_addr = alloca i32*, align 8
%b_addr = alloca i32*, align 8
%c_addr = alloca i32*, align 8
%i = alloca i32
%"alloca point" = bitcast i32 0 to i32
store i32* %a, i32** %a_addr
store i32* %b, i32** %b_addr
store i32* %c, i32** %c_addr
store i32 0, i32* %i, align 4
br label %bb1
bb:...
2008 Jan 24
2
[LLVMdev] llvm-gcc + abi stuff
...his as two doubles and goes
through memory to get it into floats instead of using vector extracts:
struct a { float w, x, y, z; };
float foo(struct a b) { return b.w+b.x+b.y+b.z; }
%struct.a = type { float, float, float, float }
define float @foo(double %b.0, double %b.1) nounwind {
entry:
%b_addr = alloca { double, double } ; <{ double, double }*> [#uses=4]
%tmpcast = bitcast { double, double }* %b_addr to %struct.a* ; <
%struct.a*> [#uses=3]
%tmp1 = getelementptr { double, double }* %b_addr, i32 0, i32 0 ;
<double*> [#uses=1]
store double %b.0, double* %tmp1, ali...
2011 Nov 03
5
[LLVMdev] LLVM problem, please do not ignore
...mentation fault:
................some rows about functions, that are not changed by my pass.
The errors occurs after it has modified a "@_Z3addii" function.
store i32 %b.0, i32* %4 and the type is ddddbbm 28
%5 = load i32* %a_addr, align 4 and the type is ddddbbm 27
%6 = load i32* %b_addr, align 4 and the type is ddddbbm 27
%7 = add nsw i32 %5, %6 and the type is ddddbbm 8
store i32 %7, i32* %0, align 4 and the type is ddddbbm 28
%7 = add nsw i32 %5, %6 is erased, ba!
%7 = load i32* %0, align 4 and the type is ddddbbm 27
store i32 %7, i32* %retval, align 4 and the t...
2011 Jan 06
0
[LLVMdev] Null address pointer in llvm.dbg.declare
...(name of the
variable, etc...), getAddress always returns NULL. Am I missing
something, or is there some other way to access the variable being
declared?
NB: this happens when processing the following bitcode:
define i32 @fun(i32 %a, float %b) nounwind {
entry:
%a_addr = alloca i32, align 4
%b_addr = alloca float, align 4
%retval = alloca i32
%0 = alloca i32
%"alloca point" = bitcast i32 0 to i32
call void @llvm.dbg.declare(metadata !{i32* %a_addr}, metadata !8), !
dbg !9
...
!8 = metadata !{i32 524545, metadata !4, metadata !"a", metadata !1, i32
3, metadata !3}...
2011 Nov 03
0
[LLVMdev] LLVM problem, please do not ignore
................some rows about functions, that are not changed by my
> pass. The errors occurs after it has modified a "@_Z3addii" function.
> store i32 %b.0, i32* %4 and the type is ddddbbm 28
> %5 = load i32* %a_addr, align 4 and the type is ddddbbm 27
> %6 = load i32* %b_addr, align 4 and the type is ddddbbm 27
> %7 = add nsw i32 %5, %6 and the type is ddddbbm 8
> store i32 %7, i32* %0, align 4 and the type is ddddbbm 28
> %7 = add nsw i32 %5, %6 is erased, ba!
> %7 = load i32* %0, align 4 and the type is ddddbbm 27
> store i32 %7, i32* %r...
2020 Aug 19
0
[PATCH 23/28] lib82596: convert from dma_cache_sync to dma_sync_single_for_device
...ef next frame to check */
- DMA_INV(dev, rfd, sizeof(struct i596_rfd));
+ dma_sync_cpu(dev, rfd, sizeof(struct i596_rfd));
while (rfd->stat & SWAP16(STAT_C)) { /* Loop while complete frames */
if (rfd->rbd == I596_NULL)
rbd = NULL;
else if (rfd->rbd == lp->rbd_head->b_addr) {
rbd = lp->rbd_head;
- DMA_INV(dev, rbd, sizeof(struct i596_rbd));
+ dma_sync_cpu(dev, rbd, sizeof(struct i596_rbd));
} else {
printk(KERN_ERR "%s: rbd chain broken!\n", dev->name);
/* XXX Now what? */
@@ -713,7 +741,7 @@ static inline int i596_rx(struct net_dev...
2020 Sep 15
0
[PATCH 11/18] lib82596: convert to dma_alloc_noncoherent
...ef next frame to check */
- DMA_INV(dev, rfd, sizeof(struct i596_rfd));
+ dma_sync_cpu(dev, rfd, sizeof(struct i596_rfd));
while (rfd->stat & SWAP16(STAT_C)) { /* Loop while complete frames */
if (rfd->rbd == I596_NULL)
rbd = NULL;
else if (rfd->rbd == lp->rbd_head->b_addr) {
rbd = lp->rbd_head;
- DMA_INV(dev, rbd, sizeof(struct i596_rbd));
+ dma_sync_cpu(dev, rbd, sizeof(struct i596_rbd));
} else {
printk(KERN_ERR "%s: rbd chain broken!\n", dev->name);
/* XXX Now what? */
@@ -713,7 +741,7 @@ static inline int i596_rx(struct net_dev...
2020 Sep 14
2
[PATCH 11/17] sgiseeq: convert to dma_alloc_noncoherent
...ef next frame to check */
- DMA_INV(dev, rfd, sizeof(struct i596_rfd));
+ dma_sync_cpu(dev, rfd, sizeof(struct i596_rfd));
while (rfd->stat & SWAP16(STAT_C)) { /* Loop while complete frames */
if (rfd->rbd == I596_NULL)
rbd = NULL;
else if (rfd->rbd == lp->rbd_head->b_addr) {
rbd = lp->rbd_head;
- DMA_INV(dev, rbd, sizeof(struct i596_rbd));
+ dma_sync_cpu(dev, rbd, sizeof(struct i596_rbd));
} else {
printk(KERN_ERR "%s: rbd chain broken!\n", dev->name);
/* XXX Now what? */
@@ -713,7 +741,7 @@ static inline int i596_rx(struct net_dev...
2012 Sep 03
1
[GIT-PULL] XFS filesystem driver
...GEST" }, \
+ { XFS_AGF_BTREEBLKS, "BTREEBLKS" }
+
+/* disk block (xfs_daddr_t) in the AG */
+#define XFS_AGF_DADDR(mp) ((xfs_daddr_t)(1 << (mp)->m_sectbb_log))
+#define XFS_AGF_BLOCK(mp) XFS_HDR_BLOCK(mp, XFS_AGF_DADDR(mp))
+#define XFS_BUF_TO_AGF(bp) ((xfs_agf_t *)((bp)->b_addr))
+
+extern int xfs_read_agf(struct xfs_mount *mp, struct xfs_trans *tp,
+ xfs_agnumber_t agno, int flags, struct xfs_buf **bpp);
+
+/*
+ * Size of the unlinked inode hash table in the agi.
+ */
+#define XFS_AGI_UNLINKED_BUCKETS 64
+
+#define XFS_AGI_MAGICNUM 0x00000001
+#define XFS_AGI_VERSIONNU...
2020 Sep 14
20
a saner API for allocating DMA addressable pages v2
Hi all,
this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs
with a separate new dma_alloc_pages API, which is available on all
platforms. In addition to cleaning up the convoluted code path, this
ensures that other drivers that have asked for better support for
non-coherent DMA to pages with incurring bounce buffering over can finally
be properly supported.
I'm still a
2020 Sep 15
32
a saner API for allocating DMA addressable pages v3
Hi all,
this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs
with a separate new dma_alloc_pages API, which is available on all
platforms. In addition to cleaning up the convoluted code path, this
ensures that other drivers that have asked for better support for
non-coherent DMA to pages with incurring bounce buffering over can finally
be properly supported.
As a follow up I
2020 Aug 19
39
a saner API for allocating DMA addressable pages
Hi all,
this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs
with a separate new dma_alloc_pages API, which is available on all
platforms. In addition to cleaning up the convoluted code path, this
ensures that other drivers that have asked for better support for
non-coherent DMA to pages with incurring bounce buffering over can finally
be properly supported.
I'm still a