Displaying 2 results from an estimated 2 matches for "b718ba79177c".
2016 Mar 09
1
[PATCH 1/2] secboot: don't use hardcoded mask to enable falcon
...th the proper
irq_mask variable.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
drm/nouveau/nvkm/subdev/secboot/base.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drm/nouveau/nvkm/subdev/secboot/base.c b/drm/nouveau/nvkm/subdev/secboot/base.c
index b718ba79177c..05c62549c39b 100644
--- a/drm/nouveau/nvkm/subdev/secboot/base.c
+++ b/drm/nouveau/nvkm/subdev/secboot/base.c
@@ -85,8 +85,8 @@ nvkm_secboot_falcon_enable(struct nvkm_secboot *sb)
/* enable IRQs */
nvkm_wr32(device, sb->base + 0x010, 0xff);
- nvkm_mask(device, 0x640, sb->irq_mask, 0x10...
2016 Feb 24
11
[PATCH v3 00/11] nouveau: add secure boot support for dGPU and Tegra
New version of the secure boot code that works with the blobs just merged into
linux-firmware. Since the required Mesa patches are also merged, this set is
the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2.
The basic code remains the same, with a few improvements with respect to how
secure falcons are started. Hopefully the patchset is better split too.
I have a