search for: b64

Displaying 20 results from an estimated 152 matches for "b64".

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2013 Mar 01
4
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...retval0) INT_PTX_SREG_NTID_X > > ( > > > > ) > > ; > > .func (.reg .b32 func_retval0) INT_PTX_SREG_NTID_Y > > ( > > > > ) > > ; > > > > // .globl examples_2E_mandelbrot_2F_square > > .func (.reg .b64 func_retval0) examples_2E_mandelbrot_2F_square( > > .reg .b64 examples_2E_mandelbrot_2F_square_param_0 > > ) > > { > > .reg .pred %p<396>; > > .reg .s16 %rc<396>; > > .reg .s16 %rs<396...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...gt; > > ) > > > ; > > > .func    (.reg .b32 func_retval0) INT_PTX_SREG_NTID_Y > > > ( > > > > > > ) > > > ; > > > > > > // .globl                        examples_2E_mandelbrot_2F_square > > > .func    (.reg .b64 func_retval0) examples_2E_mandelbrot_2F_square( > > > .reg .b64 examples_2E_mandelbrot_2F_square_param_0 > > > ) > > > { > > > .reg .pred %p<396>; > > > .reg .s16 %rc<396>; > > > .reg .s16 %rs<396>; > > > .reg .s32 %r&...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...;> > >> > ) >> > ; >> > .func (.reg .b32 func_retval0) INT_PTX_SREG_NTID_Y >> > ( >> > >> > ) >> > ; >> > >> > // .globl examples_2E_mandelbrot_2F_square >> > .func (.reg .b64 func_retval0) examples_2E_mandelbrot_2F_square( >> > .reg .b64 examples_2E_mandelbrot_2F_square_param_0 >> > ) >> > { >> > .reg .pred %p<396>; >> > .reg .s16 %rc<396>; >> >...
2013 Mar 01
1
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...; > >> > .func (.reg .b32 func_retval0) INT_PTX_SREG_NTID_Y > >> > ( > >> > > >> > ) > >> > ; > >> > > >> > // .globl examples_2E_mandelbrot_2F_square > >> > .func (.reg .b64 func_retval0) examples_2E_mandelbrot_2F_square( > >> > .reg .b64 examples_2E_mandelbrot_2F_square_param_0 > >> > ) > >> > { > >> > .reg .pred %p<396>; > >> > .reg .s16 %rc<396>; &...
2013 Mar 01
2
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
....reg .b32 func_retval0) INT_PTX_SREG_CTAID_Y ( ) ; .func (.reg .b32 func_retval0) INT_PTX_SREG_TID_X ( ) ; .func (.reg .b32 func_retval0) INT_PTX_SREG_NTID_X ( ) ; .func (.reg .b32 func_retval0) INT_PTX_SREG_NTID_Y ( ) ; // .globl examples_2E_mandelbrot_2F_square .func (.reg .b64 func_retval0) examples_2E_mandelbrot_2F_square( .reg .b64 examples_2E_mandelbrot_2F_square_param_0 ) { .reg .pred %p<396>; .reg .s16 %rc<396>; .reg .s16 %rs<396>; .reg .s32 %r<396>; .reg .s64 %rl<396>; .reg .f32 %...
2014 Nov 29
1
Unknown scheme SSHA256.HEX.b64
...ing the SSHA256 scheme in HEX format. All the password hashes are in my database (MySQL) with a {SSHA256.HEX} prefix, and I thought at first that they were working fine, but then I checked my logs and am seeing this: localhost dovecot: auth: Error: password(***@***.***): Unknown scheme SSHA256.HEX.b64 (I have replaced the email address with asterisks) I am completely flabbergasted, as I can't imagine how "SSHA256.HEX.b64" is even coming in to existence as a string. I have triple checked the database and that combination appears nowhere in it. Does anybody have any idea how that...
2007 Jul 15
1
PLAIN.B64 Password Scheme Patch Missing in Dovecot 1.0.2
Dear all, Hi. This is imacat from Taiwan. I've just downloaded the newly-released Dovecot 1.0.2, but found that the PLAIN.B64 password scheme patch seems to be missing. http://www.dovecot.org/list/dovecot/2007-May/022610.html Is there any reason for this? Thank you very much. -- Best regards, imacat ^_*' <imacat at mail.imacat.idv.tw> PGP Key: http://www.imacat.idv.tw/me/pgpkey.asc <<Woman's V...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...> ( > > ) > ; > .func聽 (.reg .b32 func_retval0) INT_PTX_SREG_NTID_X > ( > > ) > ; > .func聽 (.reg .b32 func_retval0) INT_PTX_SREG_NTID_Y > ( > > ) > ; > >聽 聽 聽 聽 聽 聽 聽 聽 // .globl聽 聽 聽 聽 聽 聽 examples_2E_mandelbrot_2F_square > .func聽 (.reg .b64 func_retval0) examples_2E_mandelbrot_2F_square( >聽 聽 聽 聽 聽 聽 聽 聽 .reg .b64 examples_2E_mandelbrot_2F_square_param_0 > ) > { >聽 聽 聽 聽 聽 聽 聽 聽 .reg .pred %p<396>; >聽 聽 聽 聽 聽 聽 聽 聽 .reg .s16 %rc<396>; >聽 聽 聽 聽 聽 聽 聽 聽 .reg .s16 %rs<396>; >聽 聽 聽 聽 聽 聽 聽 聽 .re...
2012 Jul 11
2
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
...vvm.mul.rn.f(float, float) nounwind readnone > llc -march=nvptx64 -mcpu=sm_20 test.ll -o test.ptx > cat test.ptx // // Generated by LLVM NVPTX Back-End // .version 3.0 .target sm_20, texmode_independent .address_size 64 // .globl __internal_dsmul .func __internal_dsmul( .param .b64 __internal_dsmul_param_0, .param .align 0 .b8 __internal_dsmul_param_1[8], .param .align 0 .b8 __internal_dsmul_param_2[8] ) // @__internal_dsmul { .reg .pred %p<396>; .reg .s16 %rc<396>; .reg .s16 %rs<396>; .reg .s32 %...
2020 Feb 17
3
sshd crashes
Hi, sshd crashes at below location. After compilation, when I start sshd it crashes in ?sshbuf-misc.c? file inside ?sshbuf_b64tod? function at line size_t plen = strlen(b64); The call trace is as below, Sshd main function -> sshkey_load_public -> sshkey_try_load_public -> sshkey_read -> sshbuf_b64tod During compilation a warning is thrown. Is this the trigger point for the crash? "sshkey.c", : warni...
2009 May 26
5
errors in valgrind
Hay! Has anyone come across these errors using valgrind for the oggenc tool or the encoder_example.c: ==13108== Invalid read of size 4 ==13108== at 0x4155734: _vp_offset_and_mix (in /usr/local/lib/libvorbis.so.0.4.1) ==13108==
2013 Aug 21
1
Bug in dovecot 2.2.5: segfault due to bad alignment
...pected to be a pointer to struct sha1_ctxt, a data structure which is declared in sha1.h: struct sha1_ctxt { union { uint8_t b8[20]; uint32_t b32[5]; } h; union { uint8_t b8[8]; uint64_t b64[1]; } c; union { uint8_t b8[64]; uint32_t b32[16]; } m; uint8_t count; }; Here we have with b64 one uint64_t which has on a SPARC platform an alignment requirement of 8. In consequence, struct sha1_ctxt has an ali...
2012 Nov 09
0
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
...commit? Do you think it needs a test case? Thanks, - D. dmikushin at hp2:~/forge/align0> llc -march=nvptx64 -mcpu=sm_20 align0.ll -o - // // Generated by LLVM NVPTX Back-End // .version 3.1 .target sm_20 .address_size 64 // .globl __internal_dsmul .visible .func __internal_dsmul( .param .b64 __internal_dsmul_param_0, .param .align 4 .b8 __internal_dsmul_param_1[8], .param .align 4 .b8 __internal_dsmul_param_2[8] ) // @__internal_dsmul { .reg .pred %p<396>; .reg .s16 %rc<396>; .reg .s16 %rs<396>; .reg .s32 %r<396>; .re...
2012 Jul 10
2
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...ck-End // .version 3.0 .target sm_10, texmode_independent .address_size 64 // .globl _Z5__anyi .visible .global .align 4 .b8 __local_depot0[8]; .func (.reg .b32 func_retval0) _Z5__anyi( .reg .b32 _Z5__anyi_param_0 ) // @_Z5__anyi { .reg .b64 %SP; .reg .b64 %SPL; .reg .pred %p<396>; .reg .s16 %rc<396>; .reg .s16 %rs<396>; .reg .s32 %r<396>; .reg .s64 %rl<396>; .reg .f32 %f<396>; .reg .f64 %fl<396>; // BB#0: // %entry mov...
2008 Nov 13
2
PLAIN password scheme question
Hi, ppls There is some problem with using passwd-like file and plaintext passwords within it. Let's assume we have users speaking russian. They think and remember their passwords also within russian words (they just not change keyboard layout before entering their passwords). So if the user has password like ":jgf" (meaning "ass" in russian) and passwords are stored
2007 May 11
1
Virtual User Home Directory, and APOP Clear Text Passwords
Dear all, Hi. This is imacat from Taiwan. I'm new to this list. I was migrating from Qpopper to Dovecot. (Qpopper copies the mailbox when POP3 logged in, which causes quota problem.) Generally Dovecot is nice. However, I have a few questions: 1. I have a few virtual users, and I'm not using IMAP. Do I still have to give them a writable home directory? I mean, they
2012 Jul 10
0
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...ent > .address_size 64 > > > // .globl _Z5__anyi > .visible .global .align 4 .b8 __local_depot0[8]; > > .func (.reg .b32 func_retval0) _Z5__anyi( > .reg .b32 _Z5__anyi_param_0 > ) // @_Z5__anyi > { > .reg .b64 %SP; > .reg .b64 %SPL; > .reg .pred %p<396>; > .reg .s16 %rc<396>; > .reg .s16 %rs<396>; > .reg .s32 %r<396>; > .reg .s64 %rl<396>; > .reg .f32 %f<396>; > .reg .f64 %fl<396>; > > // BB#0...
2004 Sep 05
3
ChanSpy by anthm and more...
...ZAP as with ZapScan/Barge. Native format_* files being used for moh. Reload enabled res_musiconhold. format_mp3.c that produces SLNR output to asterisk, format_slinear.c for raw headerless audio, format_base65_wav_gsm.c aka wav49 held in a base64 containers(it can read and playback from these .b64 files) All this is thanks to my employer asterlink.com and anthm. So everyone please test and provide feedback. Thanks, Brian Asterlink.com PS: More to come at a later date.
2012 Jul 10
1
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...endent > .address_size 64 > > > // .globl _Z5__anyi > .visible .global .align 4 .b8 __local_depot0[8]; > > .func (.reg .b32 func_retval0) _Z5__anyi( > .reg .b32 _Z5__anyi_param_0 > ) // @_Z5__anyi > { > .reg .b64 %SP; > .reg .b64 %SPL; > .reg .pred %p<396>; > .reg .s16 %rc<396>; > .reg .s16 %rs<396>; > .reg .s32 %r<396>; > .reg .s64 %rl<396>; > .reg .f32 %f<396>; > .reg .f64 %fl<396>; > > // BB#0:...
2018 Sep 08
0
[PATCH] maxwell,pascal: add scheduling data to shaders
...110.vp index bbfc527..85fecb7 100644 --- a/src/shader/xfrm2nv110.vp +++ b/src/shader/xfrm2nv110.vp @@ -25,58 +25,59 @@ NV110VP_Transform2[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0 wt 0x3f) (st 0x6 wt 0x1) (st 0x1 wr 0x0) ld b32 $r5 a[0x2fc] 0x0 shl $r5 $r5 0x5 ld b64 $r0 c0[$r5+0x80] -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0x2 rd 0x0 wt 0x3) (st 0xf wr 0x0 wt 0x1) ld b64 $r2 c0[$r5+0x88] st b128 a[0x70] $r0 0x0 ld b64 $r0 c0[$r5+0x90] -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0x1 wt 0x1) (st 0x1) (st 0x4) fmul ftz $r2 $r0 c0[0x0]...