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Displaying 2 results from an estimated 2 matches for "b501d226".

2016 Jan 28
2
Specifying DAG patterns in the instruction
I'm confused about how to specify DAG patterns for a given instruction Here is an example for my target class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> : ALU_RR<subOp, asmstr, [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>; def ADD : ALU1_RR<0x0, "l.add", add>; The set operation simply creates a list. The add operation
2016 Jan 29
2
Specifying DAG patterns in the instruction
....org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> > -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160129/b501d226/attachment.html>