Displaying 5 results from an estimated 5 matches for "b4934e8c551b".
2019 Jan 07
2
[PATCH RFC 3/4] barriers: convert a control to a data dependency
...ulticopy atomicity"
> for more information.
>
>
> +
> +
> In summary:
>
> (*) Control dependencies can order prior loads against later stores.
> diff --git a/arch/alpha/include/asm/barrier.h b/arch/alpha/include/asm/barrier.h
> index 92ec486a4f9e..b4934e8c551b 100644
> --- a/arch/alpha/include/asm/barrier.h
> +++ b/arch/alpha/include/asm/barrier.h
> @@ -59,6 +59,7 @@
> * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
> * in cases like this where there are no data dependencies.
> */
> +#define AR...
2019 Jan 07
2
[PATCH RFC 3/4] barriers: convert a control to a data dependency
...ulticopy atomicity"
> for more information.
>
>
> +
> +
> In summary:
>
> (*) Control dependencies can order prior loads against later stores.
> diff --git a/arch/alpha/include/asm/barrier.h b/arch/alpha/include/asm/barrier.h
> index 92ec486a4f9e..b4934e8c551b 100644
> --- a/arch/alpha/include/asm/barrier.h
> +++ b/arch/alpha/include/asm/barrier.h
> @@ -59,6 +59,7 @@
> * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
> * in cases like this where there are no data dependencies.
> */
> +#define AR...
2019 Jan 02
0
[PATCH RFC 3/4] barriers: convert a control to a data dependency
...@@ to the CPU containing it. See the section on "Multicopy atomicity"
for more information.
+
+
In summary:
(*) Control dependencies can order prior loads against later stores.
diff --git a/arch/alpha/include/asm/barrier.h b/arch/alpha/include/asm/barrier.h
index 92ec486a4f9e..b4934e8c551b 100644
--- a/arch/alpha/include/asm/barrier.h
+++ b/arch/alpha/include/asm/barrier.h
@@ -59,6 +59,7 @@
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
* in cases like this where there are no data dependencies.
*/
+#define ARCH_NEEDS_READ_BARRIER_DEPENDS 1
#defi...
2019 Jan 02
6
[PATCH RFC 0/4] barriers using data dependency
So as explained in Documentation/memory-barriers.txt e.g.
a load followed by a store require a full memory barrier,
to avoid store being ordered before the load.
Similarly load-load requires a read memory barrier.
Thinking about it, we can actually create a data dependency
by mixing the first loaded value into the pointer being
accessed.
This adds an API for this and uses it in virtio.
Written
2019 Jan 07
0
[PATCH RFC 3/4] barriers: convert a control to a data dependency
...omicity"
> > for more information.
> > +
> > +
> > In summary:
> > (*) Control dependencies can order prior loads against later stores.
> > diff --git a/arch/alpha/include/asm/barrier.h b/arch/alpha/include/asm/barrier.h
> > index 92ec486a4f9e..b4934e8c551b 100644
> > --- a/arch/alpha/include/asm/barrier.h
> > +++ b/arch/alpha/include/asm/barrier.h
> > @@ -59,6 +59,7 @@
> > * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
> > * in cases like this where there are no data dependencies.
&g...