Displaying 1 result from an estimated 1 matches for "b290e7e6".
2012 Nov 16
1
[LLVMdev] Handling segmented instruction space in backend for custom target
Hi all,
I'm building a backend for a custom target, and I'm trying to figure out
how to handle global and external target address with my architecture's
call instructions.
This arch. has 16-bit addresses into a segmented address space, and to do a
direct call I need to set both an instruction counter (IC, 10 bits wide)
and an instruction segment register (ISR, 6 bits wide). My CALL