Displaying 1 result from an estimated 1 matches for "b0cc14f1".
2019 May 06
2
RegAlloc Q: spill when implicit-def physreg is also the output reg of instruction
Hi LLVM,
I ran into a case where RegAlloc would insert a spill across instruction
that had same register for output operand and implicit-def. The effect
this had was that spill code would immediately overwrite the output
result. Is this the expected result of setting up MyInst this way? In
other words, does RegAlloc know to not insert spill in case it sees that
output reg is same as one of