Displaying 5 results from an estimated 5 matches for "avx_binop".
2011 Oct 07
4
[LLVMdev] Enhancing TableGen
...s are:
(set (type regclass:reg), (type (op (type regclass:reg), (type regclass:reg))))
So why write hundreds of patterns to express this? Using the for-loop
syntax:
// WARNING: Pseudo-code, many details elided for presentation purposes.
multiclass binop<opcode> : sse_binop<opcode>, avx_binop<opcode>;
multiclass sse_binop<opcode> {
for type = [f32, f64, v4f32, v2f64]
regclass = [FP32, FP64, VR128, VR128]
suffix = [ss, sd, ps, pd] {
def !toupper(suffix)#rr : Instr<
[(set (type regclass:$dst), (type (opcode (type regclass:$src1),...
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
...type (op (type regclass:reg), (type regclass:reg))))
>
> So why write hundreds of patterns to express this? Using the for-loop
> syntax:
>
> // WARNING: Pseudo-code, many details elided for presentation purposes.
>
> multiclass binop<opcode> : sse_binop<opcode>, avx_binop<opcode>;
>
> multiclass sse_binop<opcode> {
> for type = [f32, f64, v4f32, v2f64]
> regclass = [FP32, FP64, VR128, VR128]
> suffix = [ss, sd, ps, pd] {
>
> def !toupper(suffix)#rr : Instr<
> [(set (type regclass:$dst), (type (opcode (type...
2011 Oct 08
0
[LLVMdev] Enhancing TableGen
..., (type (op (type regclass:reg), (type regclass:reg))))
>
> So why write hundreds of patterns to express this? Using the for-loop
> syntax:
>
> // WARNING: Pseudo-code, many details elided for presentation purposes.
>
> multiclass binop<opcode> : sse_binop<opcode>, avx_binop<opcode>;
>
> multiclass sse_binop<opcode> {
> for type = [f32, f64, v4f32, v2f64]
> regclass = [FP32, FP64, VR128, VR128]
> suffix = [ss, sd, ps, pd] {
>
> def !toupper(suffix)#rr : Instr<
> [(set (type regclass:$dst), (type (opcode (type re...
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
My purpose is to eliminate copy-paste style of programming in td files
as much as possible, but only to a point that the new language
constructs do not create too much overhead/readability-downgrade.
In other words, I am targeting those low-hanging fruit of copy-paste
programmings in td files that are eliminated by a simple for-loop
syntax. The repetitive patterns I observed in PTX backend (and
2011 Oct 06
3
[LLVMdev] Enhancing TableGen
On Oct 6, 2011, at 12:42 PM, David A. Greene wrote:
> Jakob Stoklund Olesen <jolesen at apple.com> writes:
>
>> On Oct 6, 2011, at 7:59 AM, David A. Greene wrote:
>>
>>> For example, I want to be able to do this:
>>>
>>> defm MOVH :
>>> vs1x_fps_binary_vv_node_rmonly<
>>> 0x16, "movh", undef, 0,
>>>