search for: avx

I wonder why AVX is not used automatically if available at the host machine. In contrast to that, SSE41 instructions (like pmulld) are automatically used if the host machine supports SSE41. E.g. $ cat avx.ll define void @_fun1(<8 x float>*, <8 x float>*) { _L1: %x = load <8 x float>* %0...

On Thu, 24 May 2012, Pan, Wei wrote: > Very likely AVX is not enabled in your llc. This feature was enabled > just recently (late of April). I forgot to mention that I am using recent LLVM-3.1 and in principle my llc knows about avx as I have shown in the second example. But avx does not seem to be used by default. On Thu, 24 May 2012, Henning...

Hi Bruno, > Some comments: > > + // Try to synthesize horizontal adds from adds of shuffles. > + if (((Subtarget->hasSSE3()&& (VT == MVT::v4f32 || VT == MVT::v2f64)) || > + (Subtarget->hasAVX()&& (VT == MVT::v8f32 || VT == MVT::v4f64)))&& > + isHorizontalBinOp(LHS, RHS, true)) > > 1) You probably want to do something like: > > "bool HasHorizontalArith = Subtarget->hasSSE3() || > Subtarget->hasAVX()" and check it for the first condi...

.../Target/X86/X86Subtarget.cpp in X86Subtarget::AutoDetectSubtargetFeatures() Is there a bug in that function? -Hal On Thu, 24 May 2012 23:56:48 +0200 (CEST) Henning Thielemann <llvm at henning-thielemann.de> wrote: > > On Thu, 24 May 2012, Pan, Wei wrote: > > > Very likely AVX is not enabled in your llc. This feature was > > enabled just recently (late of April). > > I forgot to mention that I am using recent LLVM-3.1 and in principle > my llc knows about avx as I have shown in the second example. But avx > does not seem to be used by default. > &g...

Hi all, I have some old code using the JIT via the LLVM-3.0-C API. I want to upgrade to newer versions of LLVM. As a simple example I wrote a C program that creates the following function and calls it: ; ModuleID = 'round-avx.bc' target triple = "x86_64-pc-linux-gnu" define void @round(<8 x float>*) { _L1: %1 = load <8 x float>* %0 %2 = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %1, i32 1) store <8 x float> %2, <8 x float>* %0 ret void } ; Func...

..., there is no additional penalty for AMD processors. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chandler Carruth Sent: Monday, December 15, 2014 3:57 AM To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets FWIW, this makes sense to me. I'd be interested to hear from folks that are supporting AMD processors which do support AVX to ensure that there isn't an undue runtime penalty for these. On Sun, Dec 14, 2014 at 7:08 AM, Demikhovsky, Elena <elena.demikhovsky at...

I've been working on adding AVX to LLVM and have run across a number of questions. Here's the first one. In some ways AVX is "just another" SSE level. Having AVX implies you have SSE1-SSE4.2. However AVX is very different from SSE and there are a number of sub-features which may or may not be available on vari...

Hi all, I would like to find out whether anyone will find it useful to add an x86- specific calling convention for reducing emission of vzeroupper instructions. Current implementation: vzeroupper is inserted to any functions that use AVX instructions. The insertion points are: 1) before a call instruction; 2) before a return instruction; Background: vzeroupper is an AVX instruction; it is inserted to avoid performance penalty when transitioning between x86 AVX mode and legacy SSE mode, e.g., when an AVX function calls a SSE functi...

The output of the avx-hadd program is 3 11 7 15 Preston -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Thursday, September 22, 2011 3:14 PM To: Bruno Cardoso Lopes Cc: LLVMdev Subject: Re: [LLVMdev] Patch to synthesize x86 hadd i...

...I think that def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", "HasVectorUAMem", "true", "Allow unaligned memory operands on vector/SIMD instructions">; should be switched-ON on AVX and AVX-512 instructions because: According to the AVX spec: "Most arithmetic and data processing instructions encoded using the VEX prefix and performing memory accesses have more flexible memory alignment requirements than instructions that are encoded without the VEX prefix. Specifically,...

I should be sending up some AVX code this week. When I do this I'd like to generate some testcases to make sure we actually generate AVX code. Ideally we'd have a testcase for each AVX pattern but that's probably overkill. Still, we'd like a lot of tests, I think. Should these tests go into CodeGen/X86 or shou...

Hi, The last time the AVX backend was mentioned on this list seems to be from November 2010, so I would like to ask about the current status. Is anybody (e.g. at Cray?) still actively working on it? I have tried both LLVM 2.9 final and the latest trunk, and it seems like some trivial stuff is already working and produce...

Hello, I'm currently looking to see if Opus could benefit from AVX/AVX2 instructions and I've made some experiments optimizing xcorr_kernel_* function in celt using AVX2 intrinsics and got about 1.5x-1.6x speedup over SSE floating point version in pitch_sse.c. Have AVX optimizations been tried in Opus? Is there someone I could talk to about optimizing compute...

On Apr 30, 2009, at 3:02 PM, David Greene wrote: > I've been working on adding AVX to LLVM and have run across a number > of > questions. Here's the first one. > > In some ways AVX is "just another" SSE level. Having AVX implies > you have > SSE1-SSE4.2. However AVX is very different from SSE and there are a > number > of sub-feature...

On Tuesday 05 January 2010 13:20, Dan Gohman wrote: > On Jan 5, 2010, at 9:54 AM, David Greene wrote: > > I should be sending up some AVX code this week. When I do this > > I'd like to generate some testcases to make sure we actually > > generate AVX code. Ideally we'd have a testcase for each AVX > > pattern but that's probably overkill. Still, we'd like a lot > > of tests, I think. > &g...

I have seen some re-factoring work done to prepare for AVX support. What are the plans (time wise) to add the AVX patterns to the backend? Has anyone thought about FMA4? - Jan

On Thu, 24 May 2012, Hal Finkel wrote: > Henning, > > I believe the code that is supposed to do this is in: > lib/Target/X86/X86Subtarget.cpp in > X86Subtarget::AutoDetectSubtargetFeatures() > Is there a bug in that function? I read there: // FIXME: AVX codegen support is not ready. //if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); } It looks like the check for AVX is disabled intentionally. But if the AVX codegen is now usable, one could enable the AVX check, right?

Hello, I had talked earlier with 'Timothy B. Terriberry' <tterribe at xiph.org>, about adding support for AVX instructions in Opus, but since he appears to be busy I would like to resend this on the mailing list. I've created a pull request https://github.com/xiph/opus/pull/5 to add the testing infrastructure for the changes before adding the actual code. A draft for the rest of the code for the AVX f...

Hi Ralf, FYI, old JIT doesn't support AVX at all, no encoding info, etc... The only way to use AVX+JIT is using MCJIT, which contains the correct encoding, but unfortunately the framework isn't good yet as the old one is. On Thu, Aug 25, 2011 at 10:12 AM, Ralf Karrenberg <Chareos at gmx.de> wrote: > Hi Matt, > > I am un...

On Jan 5, 2010, at 9:54 AM, David Greene wrote: > I should be sending up some AVX code this week. When I do this > I'd like to generate some testcases to make sure we actually > generate AVX code. Ideally we'd have a testcase for each AVX > pattern but that's probably overkill. Still, we'd like a lot > of tests, I think. > > Should these tes...