Displaying 5 results from an estimated 5 matches for "avrinstrinfo".
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arminstrinfo
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
Also simple grep around related words does not show any other information...
2017 Feb 27
2
When AVR backend generates mulsu instruction ?
...b 27, 2017 at 12:41 AM, vivek pandya via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hello LLVMDevs,
>>
>> I am looking for an example for how to lower LLVM IR to mulsu kind of
>> instruction. I found that AVR back end have such instruction but
>> AVRInstrInfo.td does not define any DAG pattern for which this
>> instruction gets emitted.
>> def MULSURdRr : FMUL2RdRr<1,
>> (outs),
>> (ins GPR8:$lhs, GPR8:$rhs),
>> "mulsu\t$lhs, $rhs",
>> []>,
>> Requires<[SupportsMultiplication]>;
>> A...
2012 Jan 10
1
[LLVMdev] SelectionDAG
Hello,
I am working on a AVR backend and have a version up and running that will convert LLVM IR code to assembly code for my target. I have written a bunch of instructions from the AVR Instruction Set in AVRInstrInfo.td and not much else. In a simple test case I am attempting to compile (if that is the word you are supposed to use for this operation) test.ll:
define i8 @foo(i8 %a, i8 %b) {
entry:
%c = sub i8 %a, 5
ret i8 %c
}
with `build/Debug/bin/llc -march=avr llvm.ll -o -` and I receive:
.file "te...
2015 Jan 31
3
[LLVMdev] Encoding instructions with inconsistent formats
...stent bit that
fits.
It is:
Inconsistent bit = (postinc OR predec) OR IsPtrXReg
Where 'postinc' and 'predec' is 1 if the respective mode is used, and 0
otherwise, and IsPtrXReg is 1 if the pointer register is X.
I have tried to assign this bit using this expression with macros in
AVRInstrInfo.td, but I couldn't get it to compile (!or is not defined, and
I don't think macros will solve this situation regardless).
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2019 Mar 11
3
IsDead, IsKill
Thanks.
I saw the header comments but it wasn’t clear to me what the difference between those concepts is?
My slightly vague understanding is IsDef means that the register specified by this operand is set by the machine instruction. So I understand that to mean the MO will override that register?
Also things like early clobber, perhaps there is another document that clarifies some of these