Displaying 3 results from an estimated 3 matches for "auxclass".
2010 Sep 13
1
[LLVMdev] Multi-class register allocatable only in one class
...AddRegs followed by a move to
IntRegs. I want these copies to be removed by the coalescer in case I
have low pressure on AddRegs (because there are many of them, or
because there are few additions). If AddRegs and IntRegs are disjoint,
this wont happen, so I create another class (say "AuxClass") which
includes regs in IntRegs and AddRegs.
Now, my code for an addition would result (after isel):
<AddRegs r1> = ADDr <whatever> <whatever>
<AuxClass r2> = <AddRegs r1>
...
...
<something> = use <r2>
If pressure on AddRegs is low, coalescer wi...
2010 Sep 13
0
[LLVMdev] Multi-class register allocatable only in one class
On Sep 13, 2010, at 6:59 AM, Carlos Sánchez de La Lama wrote:
> Hi people,
>
> the LinearScan register allocator tries to use same register for both
> live intervals, if the new interval is defined by a register copy
> whose destination reg is compatible with the source register. This is
> ok. However, this "check for compatibility" is wrongly done IMHO.
>
2010 Sep 13
2
[LLVMdev] Multi-class register allocatable only in one class
Hi people,
the LinearScan register allocator tries to use same register for both
live intervals, if the new interval is defined by a register copy
whose destination reg is compatible with the source register. This is
ok. However, this "check for compatibility" is wrongly done IMHO.
Say I have regclass1 with reg A, and regclass2 with regs {A, B}, but
regclass2 defines only