Displaying 7 results from an estimated 7 matches for "attdialect".
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asmdialect
2013 Oct 22
1
[LLVMdev] System call miscompilation using the fast register allocator
...-print-after-all, and it appears all is well after 'Two-Address
instruction pass':
MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%val]
%vreg3<def> = MOV64ri64i32 4; GR64:%vreg3
%R8<def> = COPY %vreg3; GR64:%vreg3
INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R8
%vreg4<def> = LEA64r <fi#0>, 1, %noreg, 0, %noreg; GR64:%vreg4
%R10<def> = COPY %vreg4; GR64:%vreg4
INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R10
%vreg5<def> = MOV64ri64i32 3; GR64:%vreg5
%RDX<def> = COPY...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...decessors according to CFG: BB#3 BB#4
%Wd0<def> = LDD <fi#6>, 0
%R0<def> = LDD <fi#5>, 0
INLINEASM <es:int index;
for (index = 0; index < N - (N % 8); index += 8) {.
_BEGIN_KERNEL(BatchNumber);
EXECUTE_IN_ALL(> [sideeffect] [attdialect]
INLINEASM <es:connex->writeDataToArray(&C[index], /*numVectors*/ 1, /*offset*/
3);> [sideeffect] [attdialect]
%Wd1<def> = LD_D 3; mem:LD64[inttoptr (i64 3 to <8 x i64>*)](align=8)
%Wd0<def> = ADDV_D %Wd1<kill>, %Wd0<kill>...
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...40000000 / 0x80000000 =
50.00%) BB#21(0x40000000 / 0x80000000 = 50.00%)
……
BB#21: derived from LLVM BB %if.end
Live Ins: %LR %R2 %R3 %R4 %R5 %R7 %R12
Predecessors according to CFG: BB#6 BB#20 BB#9 BB#14
INLINEASM <es:ldaexd $0, ${0:H}, [$1];> [sideeffect] [mayload]
[maystore] [attdialect], $0:[regdef-ec:GPRPair],
%R8_R9<earlyclobber,def>, $1:[reguse:GPR], %R4, <!3>
%R0<def> = ANDri %R7, 1, pred:14, pred:%noreg, opt:%CPSR<def>
%R0<def> = MOVr %LR, pred:1, pred:%CPSR<kill>, opt:%noreg
%R1<def> = EORrr %R0, %LR, pred:14...
2016 Oct 29
1
Problems with Inline ASM expressions generated in the back end
...R2
%vreg6<def> = COPY %R2; GPR:%vreg6
%vreg5<def> = COPY %R1; GPR:%vreg5
%vreg12<def> = VLOAD_D_WO_IMM; MSA128D:%vreg12 dbg:IfVectorize.c:39:5
INLINEASM <es: (Param1 - Param2); // MSA_I10> [sideeffect]
[attdialect], <llc: /llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X,
Y*>::ret_type llvm::cast(Y*) [with X = llvm::ValueAsMetadata; Y = const llvm::Metadata;
typename llvm::cast_retty<X, Y*>::ret_type = const llvm::ValueAsMetadata*]: Assertion
`isa<X>(Val) &&...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...#3 BB#4
> %Wd0<def> = LDD <fi#6>, 0
> %R0<def> = LDD <fi#5>, 0
> INLINEASM <es:int index;
> for (index = 0; index < N - (N % 8); index += 8) {.
> _BEGIN_KERNEL(BatchNumber);
> EXECUTE_IN_ALL(> [sideeffect] [attdialect]
> INLINEASM <es:connex->writeDataToArray(&C[index], /*numVectors*/
> 1, /*offset*/
> 3);> [sideeffect] [attdialect]
> %Wd1<def> = LD_D 3; mem:LD64[inttoptr (i64 3 to <8 x i64>*)](align=8)
> %Wd0<def> = ADDV_D %Wd1<kill>...
2013 Jan 08
2
[LLVMdev] Inline asm bug?
...EAX
BB#0: derived from LLVM BB %entry
Live Ins: %RDI
%vreg0<def> = COPY %RDI; GR64:%vreg0
MOV32mi %RIP, 1, %noreg, <ga:@G>, %noreg, 0;
mem:ST4[@G](tbaa=!"int")
%vreg2<def> = COPY %vreg0; GR64:%vreg2,%vreg0
INLINEASM <es:> [attdialect], $0:[regdef:GR32], %vreg1<def>,
$1:[reguse:GR64], %vreg2, $2:[clobber], %EFLAGS<earlyclobber,imp-def>,
<<badref>>; GR32:%vreg1 GR64:%vreg2
%EAX<def> = COPY %vreg1; GR32:%vreg1
RET
# End machine code for function foo.
-Krzysztof
--
Qualcomm I...
2020 Feb 22
2
COPYs between register classes
Hi,
On SystemZ there are a set of "access registers" that can be copied in
and out of 32-bit GPRs with special instructions. These instructions can
only perform the copy using low 32-bit parts of the 64-bit GPRs. As
reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254,
this is currently broken due to the fact that the default register class
for 32-bit integers is