search for: atomiccmpxchginst

...p(CodeGenFunction &CGF, AtomicExpr *E, llvm::Value *Dest, LoadVal1->setAlignment(Align); llvm::LoadInst *LoadVal2 = CGF.Builder.CreateLoad(Val2); LoadVal2->setAlignment(Align); + // FIXME: The failure order needs demoting if it's AcquireRelease or Release. llvm::AtomicCmpXchgInst *CXI = - CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order); + CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order, Order); CXI->setVolatile(E->isVolatile()); llvm::StoreInst *StoreVal1 = CGF.Builder.CreateStore(CXI, Val1); StoreVal1->setA...

In the implementation of the AliasSetTracker, I see LoadInst, StoreInst, and VAArgInst are treated specially. Why aren't AtomicCmpXchgInst and AtomicRMWInst treated with similar care? Lumping together with other unknown instructions seems unnecessarily expensive in compile time. Preston -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120119/6e...

Thanks for your help John... Yup, I looked at Local.cpp even before I fired off my question to the mailing list. Take a peek here at line 464: https://github.com/llvm-mirror/poolalloc/blob/master/lib/DSA/Local.cpp Based on my understanding of this line, if AtomicCmpXchgInst does not return a pointer type, nothing gets merged. And in the example I posted, a pointer value is indeed not returned (but rather an i64 value "masking" an i32* value). And so DSA does not do the right thing in this case... -- Zvonimir -- http://zvonimir.info http://soarlab.org/ O...

Oh, no. I should have been more clear. The patch was not rejected, just lost in the daily shuffle. I already have my employer's approval to send this upstream, so I will prepare a patch against trunk this morning. > I proposed a similar patch to LLVM (left circular shift) around 10/2011. > > Parts of my patch did make it into trunk about a year after, but others > > did not.

On Monday, July 30, 2012 12:16 AM, Cameron McInally wrote: > Hey Andy, > > I proposed a similar patch to LLVM (left circular shift) around 10/2011. > Parts of my patch did make it into trunk about a year after, but others > did not. > > At that time, my solution was to add a binary operator to the IRBuilder, > since LCS fits in nicely with the other shift operators. But,

...loca, AllocaInst) // Stack management -HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs -HANDLE_MEMORY_INST(28, Store , StoreInst ) -HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) -HANDLE_MEMORY_INST(30, Fence , FenceInst ) -HANDLE_MEMORY_INST(31, AtomicCmpXchg , AtomicCmpXchgInst ) -HANDLE_MEMORY_INST(32, AtomicRMW , AtomicRMWInst ) - LAST_MEMORY_INST(32) + FIRST_MEMORY_INST(27) +HANDLE_MEMORY_INST(27, Alloca, AllocaInst) // Stack management +HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs +HANDLE_MEMORY_INST(29, Store , StoreInst ) +HANDLE_MEMOR...

Hi all, I have yet another DSA-related question :), and I would appreciate your help. Actually, the following example generates some interesting potential issues in the LLVM IR too. Here is the example in C: #define CAS(x,y,z) __atomic_compare_exchange_n(x,&(y),z,true,0,0) int main() { int *x = 0; int y = 0; int *z = x; CAS(&z,x,&y); // if (z == x) z = &y; assert(*z ==

On 11/19/2014 4:05 AM, Chandler Carruth wrote: > > On Fri, Nov 14, 2014 at 1:09 PM, Sahasrabuddhe, Sameer > <sameer.sahasrabuddhe at amd.com <mailto:sameer.sahasrabuddhe at amd.com>> > wrote: > > 1. Update the synchronization scope field in atomic instructions > from a > single bit to a wider field, say 32-bit unsigned integer. > > > I

.... Value class. Two new sub classes of Value are added: *ConstantDataArray*, an array constant *ConstantDataVector*, a vector constant. llvm-py should contain them. c. Instruction class. Four new sub classes of Instruction are added: *FenceInst*, an instruction for ordering other memory operations; *AtomicCmpXchgInst*, an instruction that atomically checks and exchanges values in a memory location; *AtomicRMWInst*, an instruction that atomically reads a memory location, combines it with another value and store the result back. *LandingPadInst *, an instruction that hold the necessary information to generate cor...