Displaying 6 results from an estimated 6 matches for "atomiccmpxchg".
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atomic_cmpxchg
2017 Apr 03
2
AtomicCmpXchg in C bindings
Hi,
is there currently a way to create a cmpxchg instruction using the C bindings?
I only found LLVMBuildAtomicRMW and LLVMBuildFence in the documentation.
Regards,
Christoph Grenz
2012 Jul 31
0
[LLVMdev] rotate
Oh, no. I should have been more clear. The patch was not rejected, just
lost in the daily shuffle.
I already have my employer's approval to send this upstream, so I will
prepare a patch against trunk this morning.
> I proposed a similar patch to LLVM (left circular shift) around 10/2011.
> > Parts of my patch did make it into trunk about a year after, but others
> > did not.
2012 Jul 31
4
[LLVMdev] rotate
On Monday, July 30, 2012 12:16 AM, Cameron McInally wrote:
> Hey Andy,
>
> I proposed a similar patch to LLVM (left circular shift) around 10/2011.
> Parts of my patch did make it into trunk about a year after, but others
> did not.
>
> At that time, my solution was to add a binary operator to the IRBuilder,
> since LCS fits in nicely with the other shift operators. But,
2012 Jul 31
3
[LLVMdev] rotate
...MORY_INST(26, Alloca, AllocaInst) // Stack management
-HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs
-HANDLE_MEMORY_INST(28, Store , StoreInst )
-HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst)
-HANDLE_MEMORY_INST(30, Fence , FenceInst )
-HANDLE_MEMORY_INST(31, AtomicCmpXchg , AtomicCmpXchgInst )
-HANDLE_MEMORY_INST(32, AtomicRMW , AtomicRMWInst )
- LAST_MEMORY_INST(32)
+ FIRST_MEMORY_INST(27)
+HANDLE_MEMORY_INST(27, Alloca, AllocaInst) // Stack management
+HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs
+HANDLE_MEMORY_INST(29, Store , Store...
2014 Aug 08
6
[LLVMdev] Plan to optimize atomics in LLVM
> I am planning in doing in IR, but with target specific-passes (such as X86ExpandAtomicPass)
> that just share some of the code
This would more normally be done via target hooks in LLVM, though the
principle is sound.
> But it must be target-dependent as for example on Power a
> seq_cst store has a fence before it, while on ARM it has a fence
> both before and after it (per
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...p(CodeGenFunction &CGF, AtomicExpr *E, llvm::Value *Dest,
LoadVal1->setAlignment(Align);
llvm::LoadInst *LoadVal2 = CGF.Builder.CreateLoad(Val2);
LoadVal2->setAlignment(Align);
+ // FIXME: The failure order needs demoting if it's AcquireRelease or Release.
llvm::AtomicCmpXchgInst *CXI =
- CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order);
+ CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order, Order);
CXI->setVolatile(E->isVolatile());
llvm::StoreInst *StoreVal1 = CGF.Builder.CreateStore(CXI, Val1);
StoreVal1->...