Displaying 8 results from an estimated 8 matches for "atomic_load_or".
2012 May 30
2
[LLVMdev] Legalizing truncating store using atomic load.
Hi,
Our target only has native support for i32 and f32 types. For data
types smaller than these, I have to custom lowering truncating store
using two atomic load instruction (which have the same semantics as
ISD::ATOMIC_LOAD_AND and ATOMIC_LOAD_OR, respectively). I run into a
problem during the legalization process, where the legalizer complains
that ISD::STORE and ISD::ATOMIC_LOAD_OR (generated at step 3 in the
following list) has different types.
Here is the lowering steps:
1. Calculate a bitmask (e.g. 0xFFFF0000 for i16) indicating where...
2012 May 31
0
[LLVMdev] Legalizing truncating store using atomic load.
Problem solved by returning the second result of the ATOMIC_LOAD_OR node...
On Wed, May 30, 2012 at 9:38 PM, Lei Mou <lei.mou.uu at gmail.com> wrote:
> Hi,
>
> Our target only has native support for i32 and f32 types. For data
> types smaller than these, I have to custom lowering truncating store
> using two atomic load instruction (which have...
2012 May 31
1
[LLVMdev] Legalizing truncating store using atomic load.
Hi Lei,
Le 31/05/2012 03:44, Lei Mou a écrit :
> Problem solved by returning the second result of the ATOMIC_LOAD_OR node...
You got the chain instead of the loaded value.
IMHO, a better solution would have been to add a Pat<> rule to match
truncstores and expand them into target store/load/and/or.
Pat : <(truncstore16 GPR:$val, MEM:$mem),
(store MEM:$mem,
(or
(and (load MEM...
2011 Apr 01
0
[LLVMdev] Assert in VerifySDNode
...C_CMP_SWAP ||
N->getOpcode() == ISD::ATOMIC_SWAP ||
N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
N->getOpcode() == ISD::ATOMIC_LO...
2011 Apr 01
2
[LLVMdev] Assert in VerifySDNode
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Duncan Sands
> Sent: Thursday, March 31, 2011 7:43 PM
> To: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Assert in VerifySDNode
>
> Hi Micah,
>
> > assert(!isa<MemSDNode>(N) && "Bad MemSDNode!");
>
> you
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...,
- AtomNode->getAlignment());
- // Remember that we legalized the chain.
- AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
- break;
- }
- case ISD::ATOMIC_LOAD_ADD:
- case ISD::ATOMIC_LOAD_SUB:
- case ISD::ATOMIC_LOAD_AND:
- case ISD::ATOMIC_LOAD_OR:
- case ISD::ATOMIC_LOAD_XOR:
- case ISD::ATOMIC_LOAD_NAND:
- case ISD::ATOMIC_LOAD_MIN:
- case ISD::ATOMIC_LOAD_MAX:
- case ISD::ATOMIC_LOAD_UMIN:
- case ISD::ATOMIC_LOAD_UMAX:
- case ISD::ATOMIC_SWAP: {
- AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
- Tmp2 = PromoteOp(Nod...