search for: atomic_load_and

Hi, Our target only has native support for i32 and f32 types. For data types smaller than these, I have to custom lowering truncating store using two atomic load instruction (which have the same semantics as ISD::ATOMIC_LOAD_AND and ATOMIC_LOAD_OR, respectively). I run into a problem during the legalization process, where the legalizer complains that ISD::STORE and ISD::ATOMIC_LOAD_OR (generated at step 3 in the following list) has different types. Here is the lowering steps: 1. Calculate a bitmask (e.g. 0xFFFF0000 for i1...

...9:38 PM, Lei Mou <lei.mou.uu at gmail.com> wrote: > Hi, > > Our target only has native support for i32 and f32 types. For data > types smaller than these, I have to custom lowering truncating store > using two atomic load instruction (which have the same semantics as > ISD::ATOMIC_LOAD_AND and ATOMIC_LOAD_OR, respectively). I run into a > problem during the legalization process, where the legalizer complains > that ISD::STORE and ISD::ATOMIC_LOAD_OR (generated at step 3 in the > following list) has different types. > > Here is the lowering steps: > 1. Calculate a bi...

....mou.uu at gmail.com> wrote: >> Hi, >> >> Our target only has native support for i32 and f32 types. For data >> types smaller than these, I have to custom lowering truncating store >> using two atomic load instruction (which have the same semantics as >> ISD::ATOMIC_LOAD_AND and ATOMIC_LOAD_OR, respectively). I run into a >> problem during the legalization process, where the legalizer complains >> that ISD::STORE and ISD::ATOMIC_LOAD_OR (generated at step 3 in the >> following list) has different types. >> >> Here is the lowering steps: &g...

...TCH || N->getOpcode() == ISD::ATOMIC_CMP_SWAP || N->getOpcode() == ISD::ATOMIC_SWAP || N->getOpcode() == ISD::ATOMIC_LOAD_ADD || N->getOpcode() == ISD::ATOMIC_LOAD_SUB || N->getOpcode() == ISD::ATOMIC_LOAD_AND || N->getOpcode() == ISD::ATOMIC_LOAD_OR || N->getOpcode() == ISD::ATOMIC_LOAD_XOR || N->getOpcode() == ISD::ATOMIC_LOAD_NAND || N->getOpcode() == ISD::ATOMIC_LOAD_MIN || N->getOpcode() == ISD::ATOMIC_LOA...

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Duncan Sands > Sent: Thursday, March 31, 2011 7:43 PM > To: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Assert in VerifySDNode > > Hi Micah, > > > assert(!isa<MemSDNode>(N) && "Bad MemSDNode!"); > > you

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...AtomNode->getSrcValue(), - AtomNode->getAlignment()); - // Remember that we legalized the chain. - AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); - break; - } - case ISD::ATOMIC_LOAD_ADD: - case ISD::ATOMIC_LOAD_SUB: - case ISD::ATOMIC_LOAD_AND: - case ISD::ATOMIC_LOAD_OR: - case ISD::ATOMIC_LOAD_XOR: - case ISD::ATOMIC_LOAD_NAND: - case ISD::ATOMIC_LOAD_MIN: - case ISD::ATOMIC_LOAD_MAX: - case ISD::ATOMIC_LOAD_UMIN: - case ISD::ATOMIC_LOAD_UMAX: - case ISD::ATOMIC_SWAP: { - AtomicSDNode* AtomNode = cast<AtomicSDNode>(Nod...