search for: atomic_load_32

...se register from this pattern. The pattern is similar to the one I use for the normal load instruction. When I tried to implement this I hit an assert during tablegenning which claims that "set" is an unknown node. If I compare this approach with Hexagon it instead matches against "atomic_load_32". I tried this too but then I don't have any destination register available and can't use the load instruction. If someone has a good picture of how to implement this I would really appreciate some advice. I suspect other targets have similar addressing modes and if so it would be nic...

...+ Requires<[HasV4T]>; >> + >> + >> + >> +def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)), >> + (i64 (LDd_GP_V4 tglobaladdr:$global))>, >> + Requires<[HasV4T]>; >> + >> +def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)), >> + (i32 (LDw_GP_V4 tglobaladdr:$global))>, >> + Requires<[HasV4T]>; >> + >> +def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)), >> + (i32 (LDuh_GP_V4 tglobaladdr:$gl...