search for: atomic_compare_swap

...0x1f7c540: i32,ch = AtomicCmpSwap 0x1f7cd00:1, 0x1f7cd00, 0x1f7c448, 0x1f7c350 <0x1f6fbe8:0> <volatile> alignment=4 Stack dump: 0. Program arguments: llc -march=arm 1. Running pass 'ARM Instruction Selection' on function '@test_compare_and_swap' I took a look at how the atomic_compare_swap implementation is done for PowerPC and X86 but got no clue how it gets from atomic_cmp_swap_32 to the target specific variant. Well, for X86 its done via a custom lowering. Any idea how the DAG entry for ARM_ATOMIC_CMP_SWAP should look like so that it is picked up by for the @atomic.cmp.swap.i32 i...

Hi, I am missing atomic operations support for the ARM backend (see PR #3887) and started trying to implement them. Since this is the first time that I work on such stuff (and llvm) I am going to take the supposedly easy route and provide an implementation that will work on Linux systems. This involves calling a special function which the kernel handles itself. Details here:

...> 1. Running pass 'ARM Instruction Selection' on function > '@test_compare_and_swap' It's hard to guess what the problem is from this. Are you able to step through the code in ARMGenDAGISel.inc to see why it fails to match? Evan > > > I took a look at how the atomic_compare_swap implementation is done > for > PowerPC and X86 but got no clue how it gets from atomic_cmp_swap_32 to > the target specific variant. Well, for X86 its done via a custom > lowering. > > Any idea how the DAG entry for ARM_ATOMIC_CMP_SWAP should look like so > that it is picke...