Displaying 4 results from an estimated 4 matches for "atomic_cmp_swap_with_success".
2014 Jun 12
6
[LLVMdev] RFC: add "cmpxchg weak" to LLVM IR
...L/SC ones by virtue of
control flow, and x86 (for example) sets ZF based on it.
Assuming that's OK, onto the DAG level. What I'd like to do is a
little odd, but makes sense I think:
1. Keep ATOMIC_CMP_SWAP with its current semantics: strong cmpxchg,
returning just the loaded value.
2. Add ATOMIC_CMP_SWAP_WITH_SUCCESS (better name suggestions welcome)
that has a second i1 value (initially) as with the IR instruction.
It's still a strong cmpxchg.
3. Expanding ATOMIC_CMP_SWAP_WITH_SUCCESS will yield an
ATOMIC_CMP_SWAP and a SETCC.
The advantage of this scheme is that existing targets can remain
mostly unchang...
2014 Jun 13
2
[LLVMdev] RFC: add "cmpxchg weak" to LLVM IR
...various targets....
I tried that originally, but quickly got into murky waters with all
the targets I've got basically no clue about.
It still could have been the best option (I started poking at Mips),
but for one particularly nasty facet: you can select ATOMIC_CMP_SWAP
in TableGen, but not ATOMIC_CMP_SWAP_WITH_SUCCESS (multiple results
and all that).
That means even getting selection back to the status quo would have
been a lot of duplicated C++ code in multiple targets, all for what's
basically a dead-end in most cases. It's far easier to make use of the
i1 before the DAG level if possible.
Anyway, th...
2016 Mar 28
0
RFC: atomic operations on SI+
...4, Custom);
>
> + // GCN CMP_SWAP needs input marshalling, and output demarshalling
> + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
> + // We can't return success/failure, only the old value,
> + // let LLVM add the comparison
> + setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
> +
> setTargetDAGCombine(ISD::FADD);
> setTargetDAGCombine(ISD::FSUB);
> setTargetDAGCombine(ISD::FMINNUM);
> @@ -1168,6 +1174,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
> SIMachineFunctionInfo *MFI =...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This