search for: atomic64_t

On Wed, Oct 07, 2015 at 01:23:07PM +0200, Arnd Bergmann wrote: > > I haven't checked all architectures, but I assume what happens is that > > 64-bit ones just #define atomic64_t atomic_long_t, so they don't have > > to provide three sets of functions. > > scratch that, I just looked at all the architectures and found that it's > just completely arbitrary, even within one architecture you get a mix > of 'long' and 'long long', plus...

On Wed, Oct 07, 2015 at 01:23:07PM +0200, Arnd Bergmann wrote: > > I haven't checked all architectures, but I assume what happens is that > > 64-bit ones just #define atomic64_t atomic_long_t, so they don't have > > to provide three sets of functions. > > scratch that, I just looked at all the architectures and found that it's > just completely arbitrary, even within one architecture you get a mix > of 'long' and 'long long', plus...

...tions do not use u64 types. >> > If they're not reliant on manipulating 64-bit quantities, then what's >> > the point of calling them atomic _64_. >> >> I haven't checked all architectures, but I assume what happens is that >> 64-bit ones just #define atomic64_t atomic_long_t, so they don't have >> to provide three sets of functions. > > scratch that, I just looked at all the architectures and found that it's > just completely arbitrary, even within one architecture you get a mix > of 'long' and 'long long', plus t...

...tions do not use u64 types. >> > If they're not reliant on manipulating 64-bit quantities, then what's >> > the point of calling them atomic _64_. >> >> I haven't checked all architectures, but I assume what happens is that >> 64-bit ones just #define atomic64_t atomic_long_t, so they don't have >> to provide three sets of functions. > > scratch that, I just looked at all the architectures and found that it's > just completely arbitrary, even within one architecture you get a mix > of 'long' and 'long long', plus t...

...> You have to wonder why atomic64_* functions do not use u64 types. > If they're not reliant on manipulating 64-bit quantities, then what's > the point of calling them atomic _64_. I haven't checked all architectures, but I assume what happens is that 64-bit ones just #define atomic64_t atomic_long_t, so they don't have to provide three sets of functions. Arnd

...> You have to wonder why atomic64_* functions do not use u64 types. > If they're not reliant on manipulating 64-bit quantities, then what's > the point of calling them atomic _64_. I haven't checked all architectures, but I assume what happens is that 64-bit ones just #define atomic64_t atomic_long_t, so they don't have to provide three sets of functions. Arnd

...why atomic64_* functions do not use u64 types. > > If they're not reliant on manipulating 64-bit quantities, then what's > > the point of calling them atomic _64_. > > I haven't checked all architectures, but I assume what happens is that > 64-bit ones just #define atomic64_t atomic_long_t, so they don't have > to provide three sets of functions. scratch that, I just looked at all the architectures and found that it's just completely arbitrary, even within one architecture you get a mix of 'long' and 'long long', plus this gem from MIPS: sta...

On Monday 19 October 2015 11:37:00 Ralf Baechle wrote: > On Wed, Oct 07, 2015 at 01:23:07PM +0200, Arnd Bergmann wrote: > > > > I haven't checked all architectures, but I assume what happens is that > > > 64-bit ones just #define atomic64_t atomic_long_t, so they don't have > > > to provide three sets of functions. > > > > scratch that, I just looked at all the architectures and found that it's > > just completely arbitrary, even within one architecture you get a mix > > of 'long' and...

On Monday 19 October 2015 09:34:15 Geert Uytterhoeven wrote: > On Wed, Oct 7, 2015 at 1:23 PM, Arnd Bergmann <arnd at arndb.de> wrote: > > static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) > > > > which truncates the result to 32 bit. > > Woops. > > See also my unanswered question in "atomic64 on 32-bit vs 64-bit (was: > Re: Add virtio gpu driver.)", which is still valid: > https://lkml.org/lkml/2015/6/28/18 > Regardi...

On Wed, Oct 07, 2015 at 12:41:21PM +0200, Arnd Bergmann wrote: > The virtgpu driver prints the last_seq variable using the %ld or > %lu format string, which does not work correctly on all architectures > and causes this compiler warning on ARM: > > drivers/gpu/drm/virtio/virtgpu_fence.c: In function 'virtio_timeline_value_str': >

The virtgpu driver prints the last_seq variable using the %ld or %lu format string, which does not work correctly on all architectures and causes this compiler warning on ARM: drivers/gpu/drm/virtio/virtgpu_fence.c: In function 'virtio_timeline_value_str': drivers/gpu/drm/virtio/virtgpu_fence.c:64:22: warning: format '%lu' expects argument of type 'long unsigned int', but

The virtgpu driver prints the last_seq variable using the %ld or %lu format string, which does not work correctly on all architectures and causes this compiler warning on ARM: drivers/gpu/drm/virtio/virtgpu_fence.c: In function 'virtio_timeline_value_str': drivers/gpu/drm/virtio/virtgpu_fence.c:64:22: warning: format '%lu' expects argument of type 'long unsigned int', but

...0UL + #ifndef __s390x__ /* Bits in the segment table address-space-control-element */ @@ -513,6 +521,67 @@ static inline int pte_file(pte_t pte) #define __HAVE_ARCH_PTE_SAME #define pte_same(a,b) (pte_val(a) == pte_val(b)) +static inline void rcp_lock(pte_t *ptep) +{ +#ifdef CONFIG_PGSTE + atomic64_t *rcp = (atomic64_t *) (ptep + PTRS_PER_PTE); + preempt_disable(); + atomic64_set_mask(_PAGE_RCP_PCL, rcp); +#endif +} + +static inline void rcp_unlock(pte_t *ptep) +{ +#ifdef CONFIG_PGSTE + atomic64_t *rcp = (atomic64_t *) (ptep + PTRS_PER_PTE); + atomic64_clear_mask(_PAGE_RCP_PCL, rcp); + preempt_...

...n locked cmpxchg8b, that may end up overwriting updates done + * by the VMCI device to the memory location. On 32bit SMP, the lock + * prefix will be used, so correctness isn't an issue, but using a + * 64bit operation still adds unnecessary overhead. + */ +static inline u64 vmci_q_read_pointer(atomic64_t *var) +{ +#if defined(CONFIG_X86_32) + return atomic_read((atomic_t *)var); +#else + return atomic64_read(var); +#endif +} + +/* + * Helper to set the value of a head or tail pointer. For X86_32, the + * pointer is treated as a 32bit value, since the pointer value + * never exceeds a 32bit value in...

...n locked cmpxchg8b, that may end up overwriting updates done + * by the VMCI device to the memory location. On 32bit SMP, the lock + * prefix will be used, so correctness isn't an issue, but using a + * 64bit operation still adds unnecessary overhead. + */ +static inline u64 vmci_q_read_pointer(atomic64_t *var) +{ +#if defined(CONFIG_X86_32) + return atomic_read((atomic_t *)var); +#else + return atomic64_read(var); +#endif +} + +/* + * Helper to set the value of a head or tail pointer. For X86_32, the + * pointer is treated as a 32bit value, since the pointer value + * never exceeds a 32bit value in...

These changes are based on Jason's latest hmm branch. Patch 1 was previously posted here [1] but was dropped from the orginal series. Hopefully, the tests will reduce concerns about edge conditions. I'm sure more tests could be usefully added but I thought this was a good starting point. [1] https://lore.kernel.org/linux-mm/20190726005650.2566-6-rcampbell at nvidia.com/ Ralph Campbell

...void); #endif /* _ASM_X86_PVCLOCK_H */ diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c index 239427c..a4f07c1 100644 --- a/arch/x86/kernel/pvclock.c +++ b/arch/x86/kernel/pvclock.c @@ -120,6 +120,11 @@ unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src) static atomic64_t last_value = ATOMIC64_INIT(0); +void pvclock_resume(void) +{ + atomic64_set(&last_value, 0); +} + cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src) { struct pvclock_shadow_time shadow; diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index b2bb5aa..5da5e53 100644...

...void); #endif /* _ASM_X86_PVCLOCK_H */ diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c index 239427c..a4f07c1 100644 --- a/arch/x86/kernel/pvclock.c +++ b/arch/x86/kernel/pvclock.c @@ -120,6 +120,11 @@ unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src) static atomic64_t last_value = ATOMIC64_INIT(0); +void pvclock_resume(void) +{ + atomic64_set(&last_value, 0); +} + cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src) { struct pvclock_shadow_time shadow; diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index b2bb5aa..5da5e53 100644...

...void); #endif /* _ASM_X86_PVCLOCK_H */ diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c index 239427c..a4f07c1 100644 --- a/arch/x86/kernel/pvclock.c +++ b/arch/x86/kernel/pvclock.c @@ -120,6 +120,11 @@ unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src) static atomic64_t last_value = ATOMIC64_INIT(0); +void pvclock_resume(void) +{ + atomic64_set(&last_value, 0); +} + cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src) { struct pvclock_shadow_time shadow; diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index b2bb5aa..5da5e53 100644...

...og.c | 16 +++++++++------- 8 files changed, 18 insertions(+), 15 deletions(-) diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h index c3edb22..34a60a8 100644 --- a/fs/btrfs/ctree.h +++ b/fs/btrfs/ctree.h @@ -1279,7 +1279,7 @@ struct btrfs_fs_info { struct btrfs_block_rsv empty_block_rsv; atomic64_t generation; - u64 last_trans_committed; + atomic64_t last_trans_committed; /* * this is updated to the current trans every time a full commit diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 2d69541..9263c6e 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -2502,7 +2502,...