Displaying 3 results from an estimated 3 matches for "atomic16".
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atomici16
2012 Sep 24
1
[LLVMdev] Heads up! New SROA implementation is going on-by-default today!
...ith a flag, or we
can temporarily turn it back off. I'm expecting to have most of the issues
folks have reported fixed today though.
> ****
>
> ** **
>
> LLVM :: Bitcode/blockaddress.ll****
>
> LLVM :: CodeGen/ARM/fast-isel.ll****
>
> LLVM :: CodeGen/X86/atomic16.ll****
>
> LLVM :: MC/ARM/arm-shift-encoding.s****
>
> LLVM :: MC/ARM/thumb-shift-encoding.s****
>
> LLVM :: MC/COFF/global_ctors_dtors.ll****
>
> LLVM :: Transforms/InstCombine/div-shift.ll****
>
> LLVM :: Transforms/LoopIdiom/non-canonical-loop.ll...
2012 Sep 22
2
[LLVMdev] Heads up! New SROA implementation is going on-by-default today!
After a lot of testing and help from Duncan, Benjamin, Joerg and others, I
think the new SROA is ready for some broader testing. I've fixed all the
crashers and miscompiles that Duncan and Joerg have been able to find
(although I'm sure there are a few left I'll tackle when there are
reports), and the LNT numbers look *really* good. Here is the latest LNT
run we got by flipping it on
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...i64 %161 to i8
- %166 = cmpxchg i8* bitcast (i64* @ull to i8*), i8 %164, i8 %165 monotonic
+ %166 = cmpxchg i8* bitcast (i64* @ull to i8*), i8 %164, i8 %165 monotonic monotonic
%167 = icmp eq i8 %166, %164
%168 = zext i1 %167 to i8
%169 = zext i8 %168 to i32
diff --git a/test/CodeGen/X86/atomic16.ll b/test/CodeGen/X86/atomic16.ll
index ec2887e..45d3ff4 100644
--- a/test/CodeGen/X86/atomic16.ll
+++ b/test/CodeGen/X86/atomic16.ll
@@ -217,7 +217,7 @@ define void @atomic_fetch_umin16(i16 %x) nounwind {
}
define void @atomic_fetch_cmpxchg16() nounwind {
- %t1 = cmpxchg i16* @sc16, i16 0, i1...