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...t; llvm website). > > It seems like I should be able to insert a custom hook using the > register class to identify the type, potentially in ISelDAGToDag.cpp or is > there a better place for this to be done? > > Thanks. > > > It sounds to me like you are looking for the AssertSext / AssertZext nodes > > -Matt > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150127/5e0b18d4/attachment.html>

I have a CopyToReg that is copying from different size types, what's the best way to change that to a zext or sext node based on signed or unsigned? I'm fairly unfamiliar with SelectionDAG process (outside of the docs on llvm website). It seems like I should be able to insert a custom hook using the register class to identify the type, potentially in ISelDAGToDag.cpp or is there a better

...VT = Node->getValueType(0); // The only "good" option for this node is to custom lower it. switch (TLI.getOperationAction(Node->getOpcode(), VT)) { @@ -710,6 +710,7 @@ Result = LegalizeOp(Node->getOperand(0)); break; } + } break; case ISD::AssertSext: case ISD::AssertZext:

...64<4>, Constant:i64<5>, Constant:i64<6>, Constant:i64<7> t16: v8i64 = add t7, t15 t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16 t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5 t22: i64 = AssertSext t20, ValueType:ch:i8 t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0> t24: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t23, undef:v8i64 t32: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<-1>, Consta...

...m studying the ARM backend on SelectionDAG, I have some following questions: 1. Each operator of SDNode in SelectionDAG is required to be defined by SDNode<ISD::XXX,XXX,XXX> in .td file, right? But several operators are not defined in .td file, why? (e.g., ISD::BR_CC, ISD::CopyToReg, ISD::AssertSext) 2. The MVT::glue value is used to ensure two nodes are scheduled together and in order. In the other word, we can’t insert any instruction of them in the scheduling, is it correct? 3. In the ARMISelLowering constructor, it sets the callback function with setLoadExtAction(ISD::SEXTLOAD, MVT...

...n of the new integer types would also require changing (at least): 1. TableGen/CodeGenTarget.cpp - recognize and generate code for the new types 2. LegalizeDAG.cpp - eliminate power-of-2 assumptions in the legalization of extload and truncstore operations. 3. SelectionDAGBuild.cpp - add types to assertsext/assertzext generation in getCopyFromRegs() 4. TargetLowering.cpp - eliminate power-of-2 assumptions in computeRegisterProperties() 5. <Arch>ISelLowering.cpp - specify actions to lower the new types and the operations that use them on all existing architectures (ouch!) Are there more? The...

...> changing (at least): > > 1. TableGen/CodeGenTarget.cpp - recognize and generate code for the new > types > > 2. LegalizeDAG.cpp - eliminate power-of-2 assumptions in the > legalization of extload and truncstore operations. > > 3. SelectionDAGBuild.cpp - add types to assertsext/assertzext > generation > in getCopyFromRegs() > > 4. TargetLowering.cpp - eliminate power-of-2 assumptions in > computeRegisterProperties() > > 5. <Arch>ISelLowering.cpp - specify actions to lower the new types and > the operations that use them on all existing arch...

...AL_ARGUMENTS: + case ISD::CALL: + case ISD::MERGE_VALUES: + case ISD::RET: + case ISD::VAARG: + case ISD::Register: + case ISD::INTRINSIC_WO_CHAIN: + case ISD::INTRINSIC_W_CHAIN: + case ISD::INTRINSIC_VOID: + case ISD::CopyToReg: + case ISD::CopyFromReg: + case ISD::AssertSext: + case ISD::AssertZext: + // Node cannot be illegal if types are legal + break; + case ISD::BUILD_VECTOR: + case ISD::INSERT_VECTOR_ELT: + case ISD::EXTRACT_VECTOR_ELT: + case ISD::CONCAT_VECTORS: + case ISD::EXTRACT_SUBVECTOR: + case ISD::VECTOR_SHUFFLE: + case I...

...It seems like I should be able to insert a custom hook using the >> register class to identify the type, potentially in ISelDAGToDag.cpp or is >> there a better place for this to be done? >> >> Thanks. >> >> >> It sounds to me like you are looking for the AssertSext / AssertZext >> nodes >> >> -Matt >> > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150127/67f2b164/attachment.html>

...AL_ARGUMENTS: + case ISD::CALL: + case ISD::MERGE_VALUES: + case ISD::RET: + case ISD::VAARG: + case ISD::Register: + case ISD::INTRINSIC_WO_CHAIN: + case ISD::INTRINSIC_W_CHAIN: + case ISD::INTRINSIC_VOID: + case ISD::CopyToReg: + case ISD::CopyFromReg: + case ISD::AssertSext: + case ISD::AssertZext: + // Node cannot be illegal if types are legal + break; + case ISD::BUILD_VECTOR: + case ISD::INSERT_VECTOR_ELT: + case ISD::EXTRACT_VECTOR_ELT: + case ISD::CONCAT_VECTORS: + case ISD::EXTRACT_SUBVECTOR: + case ISD::VECTOR_SHUFFLE: + case I...

...64<i32 (%class.F*)* @_ZN1F11isGlobalRegEv> 0, Register:i64 %X3, Register:i64 %X2, RegisterMask:Untyped, t111:1 t114: ch,glue = callseq_end t113, TargetConstant:i64<32>, TargetConstant:i64<0>, t113:1 t115: i64,ch,glue = CopyFromReg t114, Register:i64 %X3, t114:1 t117: i64 = AssertSext t115, ValueType:ch:i32 t118: i32 = truncate t117 t119: ch = lifetime.end t115:1, TargetFrameIndex:i64<0> t120: ch = lifetime.end t119, TargetFrameIndex:i64<1> t121: ch = PPCISD::RET_FLAG t120 -------------- next part -------------- A non-text attachment was scrubbed... Nam...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...AL_ARGUMENTS: + case ISD::CALL: + case ISD::MERGE_VALUES: + case ISD::RET: + case ISD::VAARG: + case ISD::Register: + case ISD::INTRINSIC_WO_CHAIN: + case ISD::INTRINSIC_W_CHAIN: + case ISD::INTRINSIC_VOID: + case ISD::CopyToReg: + case ISD::CopyFromReg: + case ISD::AssertSext: + case ISD::AssertZext: + // Node cannot be illegal if types are legal + break; + case ISD::BUILD_VECTOR: + case ISD::INSERT_VECTOR_ELT: + case ISD::EXTRACT_VECTOR_ELT: + case ISD::CONCAT_VECTORS: + case ISD::EXTRACT_SUBVECTOR: + case ISD::VECTOR_SHUFFLE: + case I...