search for: asmoperands

...herEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -594,6 +594,12 @@ struct MatchableInfo { // Compare lexicographically by operand. The matcher validates that other // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith(). for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (AsmOperands[i].Class->isUserClass() && + RHS.AsmOperands[i].Class->isUserClass() && + !AsmOperands[i].Class->isRelatedTo(*RHS.AsmOperands[i].Class)) + if (RequiredFeatures.size() != RHS.RequiredFeatures.size()) +...

...g part of the code is responsible for this from llvm/utils/TableGen/AsmMatcherEmitter.cpp (so it needs to be commented to be disabled): // The first token of the instruction is the mnemonic, which must be a // simple string, not a $foo variable or a singleton register. if (AsmOperands.empty()) PrintFatalError(TheDef->getLoc(), "Instruction '" + TheDef->getName() + "' has no tokens"); assert(!AsmOperands[0].Token.empty()); if (HasMnemonicFirst) { Mnemonic = AsmOperands[0].Token;...

...I did look at the ARMAsmParser and it seems to me that it is using a switch/case construct to change the opcode and the operands, but this construct may become too large eventually. I was wondering if it is possible to use isAsmParser only flag to call dedicated methods, like dedicated parsers for AsmOperands. Regards Vladimir ________________________________ From: Jim Grosbach [grosbach at apple.com] Sent: Wednesday, October 02, 2013 4:46 AM To: Vladimir Medic Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction Hi Vladimir, ARM does...

...nput, more targets could take advantage of integrated assembly. The longer version: For a given assembly statement, my out-of-tree target has complex instruction selection logic -- more so than the in-tree targets. This target uses variable length instructions and a laborious hierarchy of tblgen AsmOperands to do the job. Assembly and disassembly with llvm-mc and llvm-objdump work fine. As a simplification, the compiler deals almost exclusively in pseudo instructions. By x86 analogy, using pseudos to unfold a TEST32rm into MOV32rm + TEST32rr means I can skip the complex operand fitting effort neede...

Hi Vladimir, ARM does similar things for complex assembly pseudos. Have a look at the definition and use of AsmPseudoInst in the ARM backend. They’re not typically expanding to multiple “real” instructions, but that’s an implementation detail, not a constraint. -Jim On Oct 1, 2013, at 5:36 AM, Vladimir Medic <Vladimir.Medic at imgtec.com> wrote: > Hi all, > I'm working on llvm

Hi all, I'm working on llvm assembler support for Mips and for a while I'm trying to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in