Displaying 5 results from an estimated 5 matches for "asmoperandclass".
2018 May 15
1
[tablegen] anonymous def not fully instantiated
The following is an extraction from the Operand class hierarchy of Target.td. I am trying to define a parameterized version of AsmOperandClass with a passed-in bit size.
// from Target.td
class AsmOperandClass {
string Name;
}
class Operand {
AsmOperandClass ParserMatchClass;
}
// A parameterized AsmOperandClass
class myAsmOperandClass<int n> : AsmOperandClass {
string Name = "Class" # n;
}
// A concrete instan...
2015 Dec 07
2
Immediate value boundary checking
Dear all,
I have written an assembler which reads assembly instructions and produces
the equivalent binary. I have a problem. Although I set the bit range and
immediate type for an instruction like add which accepts a register and an
immediate value, I can simply overflow that value and llvm/tablegen doesn't
care!
for example for a i8imm imm value (bits<8> val) these two produce the
2015 Dec 14
2
Tablegen definition question
Hi,
That's what the DecoderMethod is for. Similarly ParserMatchClass for the
asm parser and PrintMethod for the asm printer:
def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
let ParserMatchClass = CondCodeOperand;
let DecoderMethod = "D...
2015 Dec 14
2
Tablegen definition question
Hello James,
that was also what I've planned to do but just wasn't sure. Thanks for
that.
On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk>
wrote:
> Hi,
>
> You can't nest operands like that - it must be a flattened list. So:
>
> def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm),
> (ops (i32 14), (i32
2016 Feb 08
2
LLVM Weekly - #110, Feb 8th 2016
...L259610).
* The way bitsets are used to encode type information has now been documented.
[r259619](http://reviews.llvm.org/rL259619).
* You can now use the flag `-DLLVM_ENABLE_LTO` with CMake to build LLVM with
link-time optimisation. [r259766](http://reviews.llvm.org/rL259766).
* TableGen's AsmOperandClass gained the `IsOptional` field. Setting this to 1
means the operand is optional and the AsmParser will not emit an error if the
operand isn't present. [r259913](http://reviews.llvm.org/rL259913).
* There is now a scheduling model for the Exynos-M1.
[r259958](http://reviews.llvm.org/rL259958)....