search for: asmnames

...to match register definition name (“MYReg0”) not its AsmName (“r0”). So to make this work we should write this assembly: i32 asm "nop", "~{MYReg0}" () I believe that this behavior is not correct. It works because in most back-ends register definition names and AsmNames are equal (e.g. def EAX : X86Reg<"eax", ...>) but in AMDGPU we want to have different def-names and AsmNames. This might be done by changing core LLVM code or in target-specific getRegForInlineAsmConstraint() method. What do you suppose to be better solution? Thanks, Sam ------...

...`SLLIW x1, x2, 5` I think the correct interpretation would have x1 as a 64-bit target register and x2 as the 32-bit subregister that happens to have the same AsmName as the 64-bit x2 register. Have you thought about how the HwMode/variable-sized register class proposal might interact with register AsmNames at all? This old patch that never landed <http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20141201/246835.html> is also I think related. Backends like Mips and PPC end up defining RegisterOperand with a ParserMatchClass (in the Mips case, this specified the 'parseAnyRegister'...

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set

Hello all, I was trying to install Wine on my MacBook via the Terminal. These are my system specs: odel Name: MacBook Model Identifier: MacBook2,1 Processor Name: Intel Core 2 Duo Processor Speed: 2 GHz Number Of Processors: 1 Total Number Of Cores: 2 L2 Cache (per processor): 4 MB Memory: 1 GB Bus Speed: 667 MHz Boot ROM Version: MB21.00A5.B07 SMC Version: 1.13f3 Serial Number: BLAHBLABLAH