Displaying 9 results from an estimated 9 matches for "ascmp".
Did you mean:
a_cmp
2017 Apr 03
5
[PATCH v2 0/3] nv50/ir: Preapre for running Opts inside a loop
Slowly we are getting to the point, that we miss enough optimization
opportunities as the result of our own passes.
For this we need to fix AlgebraicOpt to be able to handle mods on sources
without creating new issues.
The last patch enables looping opts.
v2: update commit author
Karol Herbst (3):
nv50/ir: fix AlgebraicOpt for slcts with mods
nv50/ir: handle logops with NOT in AlgebraicOpt
2017 Apr 03
3
[PATCH 0/3] nv50/ir: Preapre for running Opts inside a loop
Slowly we are getting to the point, that we miss enough optimization
opportunities as the result of our own passes.
For this we need to fix AlgebraicOpt to be able to handle mods on sources
without creating new issues.
The last patch enables looping opts.
Karol Herbst (3):
nv50/ir: fix AlgebraicOpt for slcts with mods
nv50/ir: handle logops with NOT in AlgebraicOpt
nv50/ir: run some
2017 Apr 03
0
[PATCH v2 2/3] nv50/ir: handle logops with NOT in AlgebraicOpt
...pp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1856,6 +1856,12 @@ AlgebraicOpt::handleLOGOP(Instruction *logop)
set0 = cloneForward(func, set0);
set1 = cloneShallow(func, set1);
+
+ if (logop->src(0).mod == Modifier(NV50_IR_MOD_NOT))
+ set0->asCmp()->setCond = inverseCondCode(set0->asCmp()->setCond);
+ if (logop->src(1).mod == Modifier(NV50_IR_MOD_NOT))
+ set1->asCmp()->setCond = inverseCondCode(set1->asCmp()->setCond);
+
logop->bb->insertAfter(logop, set1);
logop->bb->insertAfte...
2014 May 10
1
[PATCH] nv50/ir: make sure to reverse cond codes on all the OP_SET variants
...veau/codegen/nv50_ir_peephole.cpp
@@ -187,7 +187,8 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
return;
}
- if (insn->op == OP_SET)
+ if (insn->op == OP_SET || insn->op == OP_SET_AND ||
+ insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
insn->asCmp()->setCond = reverseCondCode(insn->asCmp()->setCond);
else
if (insn->op == OP_SLCT)
--
1.8.5.5
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Pretty sure there's nothing wrong with it, but it looks odd in the code.
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++--
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
...++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -973,6 +973,35 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> }
> break;
>
> + case OP_AND:
> + {
> + CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
> + if (!cmp || cmp->op == OP_SLCT)
how about if (cmp == NULL || ...) and kill the same condition later?
> + return;
> + if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
> + return;
> + if (imm0.reg.data.f32 != 1.0)
> +...
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
.../gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1023,27 +1023,53 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
case OP_AND:
{
- CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
- if (!cmp || cmp->op == OP_SLCT || cmp->getDef(0)->refCount() > 1)
- return;
- if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
- return;
- if (imm0.reg.data.f32 != 1.0)
- return;
- if (i->getSrc(t)->getInsn()->d...
2017 Apr 03
0
[PATCH v2 1/3] nv50/ir: fix AlgebraicOpt for slcts with mods
...le.cpp
index 4c92a1efb5..bd60a84998 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1797,10 +1797,10 @@ AlgebraicOpt::handleSLCT(Instruction *slct)
if (slct->getSrc(2)->asImm()->compare(slct->asCmp()->setCond, 0.0f))
slct->setSrc(0, slct->getSrc(1));
} else
- if (slct->getSrc(0) != slct->getSrc(1)) {
+ if (slct->getSrc(0) != slct->getSrc(1) || slct->src(0).mod != slct->src(1).mod)
return;
- }
- slct->op = OP_MOV;
+ slct->op = slc...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...8000000;
+
+ roundMode_CVT(i->rnd);
+
+ emitForm_MAD(i);
+}
+
+void
CodeEmitterNV50::emitIMAD(const Instruction *i)
{
code[0] = 0x60000000;
@@ -1150,9 +1213,11 @@ CodeEmitterNV50::emitSET(const Instruction *i)
code[0] = 0x30000000;
code[1] = 0x60000000;
- emitCondCode(i->asCmp()->setCond, i->sType, 32 + 14);
-
switch (i->sType) {
+ case TYPE_F64:
+ code[0] = 0xe0000000;
+ code[1] = 0xe0000000;
+ break;
case TYPE_F32: code[0] |= 0x80000000; break;
case TYPE_S32: code[1] |= 0x0c000000; break;
case TYPE_U32: code[1] |= 0x04000000; b...