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Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name

Hi all, I have the following test case: #define FLT_EPSILON 1.19209290E-7 int err = -1; int main() { float a = 8.1; if (((a - 8.1) >= FLT_EPSILON) || ((a - 8.1) <= -FLT_EPSILON)) { //I am using FLT_EPSILON to check whether (a != 2.0). err = 1; } else { err = 0; } return 0; } with -O3 optimization level clang generates already incorrect LLVM IR: ; Function Attrs:

The sign information for binary operators is available in the llvm IR by the 'nsw' (no signed wrap) flag. Seems there is no use of this flag in the code generation phase. The sign information is no more available in the selection DAG. So how can I generate different instructions for binary operators with signed/unsigned operands in the assembler (e.g. mul/mulu)? -- View this message in

Hi Arsen, On Oct 9, 2013, at 4:53 AM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > Hi all, > > I have the following test case: > #define FLT_EPSILON 1.19209290E-7 > > int err = -1; > int main() > { > float a = 8.1; > if (((a - 8.1) >= FLT_EPSILON) || ((a - 8.1) <= -FLT_EPSILON)) { //I am > using FLT_EPSILON...

On Mon, Jun 30, 2014 at 02:40:43AM -0700, Quentin Colombet wrote: > Hi Arsen, > > > > On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > > > > Hi all, > > > > I want to generate an assembly instruction for my target using target > > description representation of the instruction. The problem is that I want to > > add direct register to be chose as an output register for...

Hello All, Would anybody explain why there is not direct connection between llvm::Value and metadata nodes. If llvm::Value hold pointer to its MDNode would it cause any malfunctioning? Thanks in advance, Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/LLVM-Value-relationship-with-metadata-tp50737.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Hi all, I would like to know, why there is not direct connection between llvm::Value and metadata node? Thanks, Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/LLVM-debug-information-tp50695.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Thanks for your reply David. Would you please clarify what do you mean by saying: David Chisnall-5 wrote > Increasingly, it seems that nodes have several metadata nodes and so they > are all paying the time penalty for the lookup. Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/LLVM-Value-relationship-with-metadata-tp50737p50793.html Sent from the LLVM - Dev

Hello All, I am interested in Control Dependence Graph building using the CFG and Dominance Frontier provided by corresponding passes. Just wandering whether LLVM provides some kind of pass or builder which will generate the Control Dependence Graph? Thanks, Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/Control-Dependence-Graph-builder-tp56687.html Sent from the

Hello Alexandra, I have the same problem what you tell here related to the loop condition(s). You have wrote this article 3 years ago and I just want to know how do you resolve this problem. I am also thinking to keep all BBs representing a condition in a separate vector as it is done with the body's BBs (sure they will not be kept in body's list). Could you please tell your solution?

Hello, I have a need to change the parameter type of llvm.lifetime.start/end intrinsic functions to get other defined type, but i do not want to replace the current definition of the intrinsic function with the new definition. Is there a way, to do such things for a specific target? If the only way to do this is to create a separate file for my target and write there a target specific

Hi all, I have found that in LLVM Front-End there are a lot of codes containing a hard-coded i8 type generation (with using of the function llvm::Type::getInt8Tyand()) and a lot of computations (basically in LLVM passes) which consider that the char size provided by the target is an 8 bit. So if I want to add a support for a target which considers 16 bit for characters I have to change all this

Hi everyone, How would you pass a string container from TargetISelLowering phase to the TargetInstPrinter phase? May be I have missed something essential, but currently seems they don't have shared class or something like that, and currently I am thinkin to initialize container in TargetTargetMachine, then pass it to the TargetInstPrinter using TargetMCAsmInfo class or something like this. I

Hi Tim, Thank you for your response. I need that immediate value latter to concatenate to registers' names (which I am doing during assembly printing). Also just Updating some status for my questioin: I have continued with using *Defs* list. It allows me to keep Registers as an implicit operands of /*MachineInstr*/ and later during its lowering pass them to the /*MCInstr*/. Now seems I need

Hi all, I would like to be sure that Tablegen still does not support completely separate multiple instruction generation, and the only way is to write costume code (may be in TargetISelDAGToDAG class) to get the needed result. Dear Tom, do you found other solution (using Tablegen tool) for this? Thanks, Arsen -- View this message in context:

Hi all, My question is related to the register usage in instruction definition at TARGETInstrInfo.td file. I have defined new Target with it Registers and instructions. Now I need to generate an instruction like: mov MYREG1_NAME, MYREG2_NAME for the built-in function taking one constant integer argument, such as "__builtin_my_function_name(88)" I wondering whether it is possible

Thank you John. Actually the opt tool (from LLVM 3.2 version) can generate the needed graphs (with pass "-domfrontier"). But I just want to surely know is there some pass or builder which can be integrated somehow so it will be possible directly to generate CDG? -- View this message in context: http://llvm.1065342.n5.nabble.com/Control-Dependence-Graph-builder-tp56687p56689.html Sent

Dear all. I have a problem with the following situation: I want to handle an intrinsic function in a specific way. The prototype of my function is: "/int my_intrinsic_name()/" So I want to generate a move instruction which should use two register type operands: "/mov R1, R2/" For this purpose I assume that the instruction definition in the TargetInstrInfo.td file